SpeakHDL utilizes VHDL aliases for two reasons:
1) to provide user defined names for I\O signals declared at the port
2) to allow the developer to create meaningful names for framework signals
Part of the SpeakHDL Productivity Strategy is to use a common port interface for all application modules. The approach is effective from a scripting standpoint, however, it requires the use of the generic signals names, sm_input, sm_output, and sm_io at the port interface. By using VHDL aliases, SpeakHDL provides the ability for a developer to define their own I/O signal names while also utilizing the common port interface. The user defined name becomes an alias to a slice of either sm_input, sm_output or sm_io depending on the mode of the signal. In this way, SpeakHDL is able to concatenate all user defined I/O signals with the same mode together and keep generic signal names at the port. For example, app_module_2.vhd has (4) input signals, each of which are aliased to a concatenated slice of sm_input as shown below.
When the 'ok' command is given, SpeakHDL firsts sorts the I/O signal names for each mode alphabetically then assigns a concatenation of aliased ranges to either sm_input, sm_output, or sm_io to each name. This ensures some form of uniqueness on structure of a config file and ensures that I/O signal names that appear first alphabetically will occupy the lowest bits of the aliased sm_input, sm_output, or sm_io signal range.
Aliases also provide a mechanism for creating more semantic names for framework signals. Due to the fact that the data structure returned from a procedure call is quite large, it is often times very convenient to use an alias with a shorter name for the entire signal or a range of bits. SpeakHDL handles aliases for both I/O signals and framework signals as entries in the config file. The syntax for an alias declaration is the same as standard VHDL. Aliases could either be placed in the global section where all application modules will have access to the declaration or a local section where only one application module has access to the declaration. By default, SpeakHDL sets up a global alias of srr as an alias to the state register record and state_reg as an alias the integer valued state register:
In addition to aliases, SpeakHDL offers limited support for declaration of VHDL constants for std_logic, std_logic_vector and integer types. Constant declaration are only allowed to be declared in the local section of the config file. The syntax for a constant declaration is the same as standard VHDL.