APPLICATION MODULE STRUCTURE

Overview

In SpeakHDL every application module is constrained to have an identical VHDL file structure which includes:

1. A Fixed Port Interface
2. A single VHDL process statement
3. A standardized layout for various coding constructs
   

As shown below, most of the VHDL code structure that is used for development is specified as a parametrized template file. Most of the parameters values are calculated by the parser when the ok command is given. In addition, the layout of the Application Module .vhd file structure was carefully chosen in order to maximize coding productivity. This means that constructs that are changed most often by the user were selectively placed at the bottom of the file.

When using a text editor with functionality that can automatically scroll to the bottom of the file, we are able to maximize the limited viewing area offered by most computer monitors and have access the most interesting data. In addition, having the bottom of the file most accessible allows for the use of Hotkey Sequence Input.

Application Module File Template:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.user_defs_pkg.all;
use work.sm_api_pkg.all;
<USER_PACKAGES>
 
--===========================================================================================
entity <MODULE_NAME> is
 
    generic (this_sm              : integer :=  <MODULE_INDEX>);
    port (
              clk                 : in std_logic;
              reset               : in std_logic;
              sm_input            : in std_logic_vector(<SM_INPUT_HIGH> downto 0);
              sm_output           : out std_logic_vector(<SM_OUTPUT_HIGH> downto 0);
              sm_io               : inout std_logic_vector(<SM_IO_HIGH> downto 0);
              next_state_rec      : out nsr_array(0 to <SM_NSR_HIGH>);
              state_reg_rec       : in srr_array(0 to <SM_NSR_HIGH>)
         );
 
end entity <MODULE_NAME>;
--===========================================================================================
 
architecture arch of <MODULE_NAME> is
 
<COMPONENT_DECLARATIONS>
 
<DECLARATIONS>
 
begin
--===========================================================================================
 
<COMPONENT_INSTANTIATIONS>
 
<DIRECT_INSTANTIATIONS>
--===========================================================================================
 
<SIGNAL_ASSIGNMENTS>
 
--===========================================================================================
 
process(state_reg_rec)
 
begin                           <APPLICATION_STATUS>
 
<PARALLEL_PROCEDURES>
 
<SEQUENTIAL_PROCEDURES>
end process;
 
end architecture arch;
--===========================================================================================
<HOTKEY_SEQUENCE_INPUT>

Table of Template Parameters

Parameter	Description	Input
MODULE_NAME	VHDL entity	[calculated by parser] from file name
MODULE_INDEX	VHDL generic index	[calculated by parser] from procedure calls
SM_INPUT_HIGH	Number of Input -1 utilized by Application Module	[calculated by parser] from config file
SM_OUTPUT_HIGH	Number of Outputs -1 utilized by Application Module	[calculated by parser] from config file
SM_IO_HIGH	Number of IO -1 utilized by Application Module	[calculated by parser] from config file
SM_NSR_HIGH	Number of Resources -1 utilized by Application Module	[calculated by parser] from procedure calls
USER_PACKAGES	VHDL package	input by user via config file
COMPONENT_DECLARATIONS	VHDL component declaration	input by user (non-direct, copy and paste declaration)
DECLARATIONS	VHDL Declarations	[inferred by parser] via user signal assignment and state machine construction
COMPONENT_INSTANTIATIONS	component instance	[inferred by parser]*
DIRECT_INSTANTIATIONS	direct instantiation instance	[inferred by parser]*
SIGNAL_ASSIGNMENTS	WHEN-ELSE statements	input by user
APPLICATION_STATUS	user status feedback	[output by parser] from parser
PARALLEL_PROCEDURES	procedures placed outside any state machine	input by user
SEQUENTIAL_PROCEDURES	procedures placed inside state machine state	input by user
HOTKEY_SEQUENCE_INPUT	last line of text editor used as input by user	input by user

Notes and Warnings

Note

*SpeakHDL automatically infers the first component instantiation based on whether there is a component declaration present. Subsequent components with the same declaration must be added by the user.

Note

Notepad++ as automatic scrolling capability to enable:
From the main menu. Go to Settings -> Preferences -> MISC.
File Status Auto-Detection Menu -> Pull-down Enable. Check Update silently. Check Scroll to the last line after update.

Todo:

add these instructions to a quick start