Overview
The TIME_COUNTER procedure call is used to configure a dual counter which is internally chained together inside the framework module. Both the divide_counter and the delay_counter can be configured individually or in tandem. Configuration is done by specifying count values or timing function for the framework delay counter (slower counter), or divide counter (faster counter), or both. In many use cases, the delay_count value is given as an integer, and the divide_count value is given as a timing function indicating either us, ms, or seconds.
When both counters are enabled, the faster divide counter increments every clock cycle and the rolls over when the count value reaches divide_count - 1. The divide_done strobe is then used to enable and increment the slower delay counter. When the delay counter value reaches delay_count - 1, then both counters assert their respective done signals for one clock cycle and the count values rollover to zero on the next rising edge of the clock.
The TIME_COUNTER will be enabled for incrementing when the enable parameter is either:
- a std_logic type signal with value equal to '1'
- a boolean expression evaluating to True
It should be noted that the TIME_COUNTER procedure call cannot cause a state machine transition, and the delay counter and divide counter never hold the same count between clock cycles.
The counters are counting upwards or explicitly set to zero when the optionalenable} parameter is set to '0' or FALSE. This is in distinct contrast to the use case of TRANSITION which also uses the delay counter and divide counter, except the TRANSITION procedure call does not have an explicit reset mechanism but is allowed to cause a state machine transition. This separation of capability is by design, provides better semantics, and reduces debugging time than if one procedure call could perform all functions.
Usage Example
Example API Call(s):
TIME_COUNTER( 5, us(3.3), next_state_rec, state_reg_rec );
TIME_COUNTER( 100, -1, next_state_rec, state_reg_rec, input_sig(0) = '1' );
Call Data [ 5 parameters (4 mandatory, 1 optional) ]
- Parameters
-
[in] delay_count [1] integer final value (minus one) before rollover (slower counter) [in] divide_count [2] integer final value (minus one) before rollover (faster counter) [out] next_state_rec [3] [in] state_reg_rec [4] [in] enable* [5] (optional) std_logic or boolean expression
Return Data
- Parameters
-
[in] state_reg_rec(M).delay.value [1] [integer] value returned from framework
[in] state_reg_rec(M).delay.done [2] [std_logic] value asserted before rollover (strobe signal)
[in] state_reg_rec(M).divide.value [3] [integer] value returned from framework [in] state_reg_rec(M).divide.done [4] [std_logic] value asserted before rollover (strobe signal)
Command Reference
Voice and Hotkey Commands:
- See also
- Time Counter Commands
Command Parameter Mapping
- Parameters
-
[in] delay_count [1] "(delay|count) <integer>" [in] divide_count [2] "divide <integer>" [in] enable [5] "enable [when] (<std_logic>|<boolean>)"
Command Return Data
- Parameters
-
[in] state_reg_rec(M).delay.value [1] [integer] "delay count" [in] state_reg_rec(M).delay.done [2] [std_logic] "delay (done|strobe)"
[in] state_reg_rec(M).divide.value [3] [integer] "divide count" [in] state_reg_rec(M).divide.done [4] [std_logic] "divide (done|strobe)"
Notes and Warnings
- Note
- When the enable parameter is set to '0' or evaluates to False, both the delay_counter and divide_counter will be reset to zero on the next clock cycle.
- The TIME_COUNTER functionality can be also be achieved by using two CONFIGURE_COUNTER calls with a chain optional parameter.
- A delay_count or delay_count parameter value of -1, 0, or 1 are taken to mean 1 clock cycle.
- Warning
- Both the TIME_COUNTER and the TRANSITION procedure call use the same delay_counter and divide_counter hardware. If both procedure calls need to be utilized, they should be placed on separate a separate resource domain.
Procedures | |
| TIME_COUNTER( delay_count: integer divide_count: integer signal next_state_rec: out NSR state_reg_rec: in SRR enable: std_logic ' 1 ' ) | |
| TIME_COUNTER( delay_count: integer divide_count: integer signal next_state_rec: out NSR_ARRAY state_reg_rec: in SRR_ARRAY enable: std_logic ' 1 ' ) | |
| 0verloaded for array next_state_rec and state_reg_rec. Optional std_logic or boolean enable. | |