vga_controller_example

Config File:

[global]
clk_pin = E3
reset_pin = U9
sys_clk_freq = 100E6
reset_polarity = '1'
data_width = 32
control_width = 32
default_signal_polarity = '1'
default_voltage_standard = 3.3V
pinout_filename = PINOUT.xdc
default_time_units = ms
alias srr is state_reg_rec(0);
alias state_reg : integer is state_reg_rec(0).state_reg;
 
[vga_controller]
output blue(4) = B7, C7, D7, D8
output green(4) = C6, A5, B6, A6
output h_sync = B11
output red(4) = A3, B4, C5, A4
output v_sync = B12
 

VHDL Code:

library ieee;                                                                 -- version: beta
use ieee.std_logic_1164.all;                                                  -- lic: non-commercial
use ieee.numeric_std.all;                                                     -- user: local
use ieee.std_logic_unsigned.all;
use work.user_defs_pkg.all;
use work.speakhdl_api_pkg.all;
 
--==============================================================================================
entity vga_controller is
 
    generic (this_sm              : integer :=  -1);                
    port (
              clk                 : in std_logic;                             -- clock: E3, 100MHz
              reset               : in std_logic;                             -- reset: U9, '1'
              sm_input            : in std_logic_vector(-1 downto 0);         -- num inputs:  0
              sm_output           : out std_logic_vector(13 downto 0);        -- num outputs: 14
              sm_io               : inout std_logic_vector(-1 downto 0);      -- num io:      0
              next_state_rec      : out nsr_array(0 to 0);
              state_reg_rec       : in srr_array(0 to 0)                      -- num rsc:     1
         );
 
end entity vga_controller;
--==============================================================================================
 
architecture arch of vga_controller is
 
    alias blue : std_logic_vector(3 downto 0) is sm_output(3 downto 0);        -- output B7,C7,..
    alias green : std_logic_vector(3 downto 0) is sm_output(7 downto 4);       -- output C6,A5,..
    alias h_sync : std_logic is sm_output(8);                                  -- output B11
    alias red : std_logic_vector(3 downto 0) is sm_output(12 downto 9);        -- output A3,B4,..
    alias v_sync : std_logic is sm_output(13);                                 -- output B12
    alias srr is state_reg_rec(0);                                             -- alias (global)
    alias state_reg : integer is state_reg_rec(0).state_reg;                   -- alias (global)
    signal h_enable : std_logic;  
    signal v_enable : std_logic;  
    signal video_on : std_logic;  
 
begin
--==============================================================================================
                                                                               -- output signals
    blue(3 downto 0) <= (others => '0');
 
    green(3 downto 0) <= (others => '0') when (video_on = '0') else
                         (others => '1') when (to_unsigned(srr.counter(1).value, 7)(6) = '0') else
                         (others => '0');
 
    h_sync <= '0' when (srr.counter(0).value < us(5.12)) else
              '1';
 
    red(3 downto 0) <= (others => '0') when (video_on = '0') else
                       (others => '1') when (to_unsigned(srr.counter(1).value, 7)(6) = '1') else
                       (others => '0');
 
    v_sync <= '0' when (srr.counter(1).value < ms(0.064)) else
              '1';
 
--==============================================================================================
                                                                               -- local signals
    h_enable <= '0' when (srr.counter(0).value < us(5.76)) else
                '0' when (srr.counter(0).value > us(31.36)) else
                '1';
 
    v_enable <= '0' when (srr.counter(1).value < ms(0.992)) else
                '0' when (srr.counter(1).value > ms(16.352)) else
                '1';
 
    video_on <= '1' when (h_enable = '1' and v_enable = '1') else
                '0';
 
--==============================================================================================
                                                                              -- units: ms, '1'
process(state_reg_rec)                                                        -- hotkey only
 
begin                               -- Log Status: OK     
 
    --------------------------------------------------------------------------------------------
    ---------------------------sys_clk 100MHz active resource 0 state -1------------------------
    --------------------------------------------------------------------------------------------
    RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );
    --------------------------------------------------------------------------------------------
    CONFIGURE_COUNTER( 0, us(32.0), no_trans, next_state_rec, state_reg_rec );
    CONFIGURE_COUNTER( 1, ms(16.672), no_trans, next_state_rec, state_reg_rec );
 
end process;
 
end architecture arch;
--==============================================================================================
 

See also

led_blink_example

sseg_display_example

uart_loopback_example