What is SpeakHDL

What is SpeakHDL?

FPGA Design Productivity and Added Value

SpeakHDL is an FPGA Design Entry Tool

SpeakHDL is an FPGA Design Entry Tool:

SpeakHDL is a command based FPGA design entry tool focused on ease of use and FPGA rapid prototyping. The novel approach of SpeakHDL is that it utilizes both procedural programming techniques and user voice or hotkey commands to increase FPGA design productivity. SpeakHDL utilizes an API library of procedure calls implemented in native VHDL that generalize a state machine interface as a hardware abstraction layer.  It then uses this hardware abstraction layer to interconnect components and implement sequential logic circuits such as state machines, fifos, counters, ect.

Under the hood, SpeakHDL utilizes a patented design strategy with a flat design architecture which makes procedural programming useful for synthesizable FPGA design.  The design pattern, which is essentially a hybrid between a facade design pattern and a state design pattern , masks much of the FPGA design complexity.  However, the design pattern can be somewhat tedious to implement using traditional RTL coding techniques.  SpeakHDL adds many usability features to the design pattern. It provides a way to map voice commands and hotkey sequences to VHDL procedure calls without imposing a steep learning curve on the user.

SpeakHDL is a Transparent Addition to Text Editors

SpeakHDL is a Transparent Addition to Text Editors:

From a users stand point, SpeakHDL is essentially just a background application running along side a text editor that enforces a specific VHDL coding structure.  Consider the normal FPGA design flow, where a text editor is used to create some .vhd files which are subsequently used as input to a simulation and synthesis tool chain.

SpeakHDL does not change that flow. SpeakHDL serves an entry point for scripting which helps speed up development time. User commands can either be given by voice or by typing on the last line of the editor. When a command is recognized, SpeakHDL writes to one or more design files and updates the text editor with the new file structure.

One of main advantages of using SpeakHDL over many GUI based FPGA design approaches is portability.  All that is needed to run SpeakHDL is a text editor with a minimal set of features and an API library targeted for a vendor specific toolchain.  Because the output of SpeakHDL are just text files containing native VHDL source code, it is possible to use SpeakHDL in a browser based text editor with no software installation or OS dependencies.

SpeakHDL Provides Meaningful Semantics

SpeakHDL Provides Meaningful Semantics

SpeakHDL's use of user commands and procedural programming is not only productive for FPGA design, but also provides more meaningful semantics than a traditional RTL coding style.  Consider the SpeakHDL command sequence and the resultant VHDL code:

Voice Commands
  1. "restart from scratch"
  2. "configure state machine"
  3. "transition"
  4. "count thirty-three point two micro-seconds"
  5. "goto state one"
  6. "next state"
  7. "read fifo data"
  8. "count one twenty eight"
  9. "next state"
  10. "conditional transition"
  11. "goto state zero"
  12. "when shared register one equal to one"
  13. "ok"
Hotkey Commands
  1. restart
  2. sm
  3. tr
  4. count 33.2us
  5. goto 1
  6. n
  7. rf
  8. count 128
  9. n
  10. ct
  11. goto 0
  12. when shared_register(1) = 1
  13. ok

process(state_reg_rec) -- hotkey only
begin -- Log Status: OK
---------------------------sys_clk 100MHz active resource 0 state -1------------------------
RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );
sm0: case (state_reg) is
when 0 =>
TRANSITION( 1, us(33.2), 1, next_state_rec, state_reg_rec );
when 1 =>
READ_FIFO_DATA( this_sm, srr.fifo_data_ready, 128, 2, next_state_rec, state_reg_rec );
when 2 =>
CONDITIONAL_TRANSITION( 0, srr.shared_register(1) = '1', 0, next_state_rec, state_reg_rec );
when 3 =>
when others =>
end case;
end process;
end architecture arch;

SpeakHDL Provides Meaningful Semantics

SpeakHDL Provides Meaningful Semantics

One could argue that any developer with a modest software background could figure out the intent of the VHDL code. The use of the TRANSITION procedure call handles state transitions which are only a function of time and the CONDITIONAL_TRANSITION procedure call replaces the need for an ' if-then-else ' statement when a state transition is dependent on a signal.

Command based programming provides a mechanism to easily learn the API without generating VHDL syntax errors.  It eliminates the need to memorize the number, order, and data types of the parameters for each procedure call.

SpeakHDL Increases HDL Code Reuse

SpeakHDL Increases HDL Code Reuse:

Traditional HDL code reuse is obtained primarily through the use of components. Component reuse is ideal for FPGA developers wishing to reuse local functionality. However, it is the integration and control of these components that often leads to an adhoc FPGA design with tightly coupled modules requiring a massive amount of signals declarations.

SpeakHDL adds to the traditional component reuse model by allowing for architectural reuse within an FPGA design.  SpeakHDL provides a reusable framework that handles control and communication between application modules in a uniform way through the use of overloaded procedure calls .  This improves VHDL code readability, loosens the coupling between application modules, and dramatically reduces the number of signals that need to be declared for interconnection purposes.

SpeakHDL Productivity Strategy

SpeakHDL Productivity Strategy

SpeakHDL's approach to FPGA design productivity is to provide the developer with an API and an architectural framework that can achieve more code reuse than traditional FPGA design strategies.

SpeakHDL makes use of proven software abstraction techniques to hide FPGA design complexity by:

  • Using a common port interface for all application modules that use the design pattern
  • Utilizing a single VHDL process model
  • Using procedural programming for high level data flow
  • Abstracting the clock signal and reset signals into a larger data structure
  • Forcing a separation between sequential logic and combinatorial  logic
  • Using commands to avoid VHDL syntax errors invoke backend scripting
  • Treating testbench development in the same manner as developing any other application module

SpeakHDL has Academic Value

SpeakHDL has Academic Value

SpeakHDL's modification of a software design pattern to make it suitable for synthesizable HDL code development is deserving of some academic merit of its own. Long before it became practical to create a new programming language to address a specific problem set, software developers turned to design patterns to address many of their challenges.  SpeakHDL shows that using a design pattern approach can be very effective not only for developing software but also in FPGA hardware development.

In addition, the VHDL language has historically been criticized as being overly verbose. This is mainly due to the language being strongly typed.  Ironically enough, it is the strong type system of VHDL that makes the use of overloaded procedure calls even possible.  SpeakHDL takes advantage of the languages native support for overloading procedure calls which is a feature that is seldom used in synthesizable HDL code. When using a design pattern, VHDL can actually be very a succinct and readable language for the same reason which makes it verbose.

SpeakHDL has Academic Value