docs/app__module__1_8vhd.html

library ieee;                                                                 -- version: beta

use ieee.std_logic_1164.all;                                                  -- lic: non-commercial

use ieee.numeric_std.all;                                                     -- user: guest

use ieee.std_logic_unsigned.all;

use work.user_defs_pkg.all;

use work.speakhdl_api_pkg.all;


--==============================================================================================

entity app_module_1 is


    generic (this_sm              : integer :=  -1);

    port (

              clk                 : in std_logic;                             -- clock: E3, 100MHz

              reset               : in std_logic;                             -- reset: U9, '1'

              sm_input            : in std_logic_vector(1 downto 0);          -- num inputs:  2

              sm_output           : out std_logic_vector(3 downto 0);         -- num outputs: 4

              sm_io               : inout std_logic_vector(-1 downto 0);      -- num io:      0

              next_state_rec      : out nsr_array(0 to 0);

              state_reg_rec       : in srr_array(0 to 0)

         );


end entity app_module_1;

--==============================================================================================


architecture arch of app_module_1 is


    alias some_input_name : std_logic_vector(1 downto 0) is sm_input(1 downto 0);-- input H14,B9

    alias some_output_name : std_logic_vector(3 downto 0) is sm_output(3 downto 0);-- output A3,R5,..

    alias srr is state_reg_rec(0);                                             -- alias (global)

    alias state_reg : integer is state_reg_rec(0).state_reg;                   -- alias (global)


begin

--==============================================================================================

                                                                              -- units: ms, '0'

process(state_reg_rec)                                                        -- hotkey only


begin


    --------------------------------------------------------------------------------------------

    ---------------------------sys_clk 100MHz active resource 0 state -1------------------------

    --------------------------------------------------------------------------------------------

    RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );

    --------------------------------------------------------------------------------------------


end process;


end architecture arch;

--==============================================================================================