SpeakHDL makes every attempt to focus on simplicity and practicality when configuring an FPGA. This is done by imposing some standardized structure on a coding problem that otherwise be ad-hoc in nature. Attaining simplicity (for both the end user and the parser) comes at the cost of sacrificing some flexibility in naming conventions on various VHDL coding constructs. The rationale for the naming conventions is two-fold:
Some naming conventions utilized by SpeakHDL are quite intuitive as to the design choice. For example, an application module VDHL entity name must be the same as the corresponding .vhd file. However, the primary reason for introducing naming conventions is to aid in coding productivity. SpeakHDL removes the necessity for the end user to manually declare signals assignments while coding. The use of meaningful signal naming conventions give the parser unambiguous hints as to the signals type. Thus, the declaration for signal assignments and state machine state names can be automatically declared by the parser.
Shown below is a list of naming conventions that SpeakHDL uses for various design elements.
| Parameter | Convention Used |
|---|---|
| application module entity name | must be the same as the design filename without the .vhd extension |
| state machine state name | must be either an integer literal or name must begin with st_ prefix |
| testbench file name | must be the same name as the application file used as the DUT except with a _tb suffix |
| std_logic_vector signal assignment assignment name | must be a validVHDL identifier} with a range (X downto Y) |
| integer signal assignment name | must be a valid VHDL identifier with _i suffix |
| resource name | must be referenced as this_sm* for the same application module and the VHDL entity name for another application module |
| resource offset name | must be the same as the resource name with _<integer> suffix |