The following commands create three general purpose counters that all count to 10. The
done
signal of the lower indexed counters are used as the
enable
of the higher index counter.
The following commands configure the divide counter (faster counter) to count 1.1us and the slower delay counter to count to 3. The net affect is a 3.3 us counter that rolls over and starts again, but outputs strobes every 1.1us. In order to cut down on simulation time, the clock frequency was dropped from 100MHz to 10MHz.
The following commands configure two framework counters. One counter operates on the default
sys_clk
domain (100MHz) while the other operates on a user specified 50MHz clock domain.
Using the following commands, application module ' writer.vhd ' streams data from counter(0) into a fifo and application module ' reader.vhd ' reads the data from the fifo. Note that the fifo_write_enable signal is used as the enable for the counter.