Overview
The READ_FIFO_DATA procedure call sets up a channel for point to point data to be received from another application module. The data could be transferred either using to a read buffer which uses flow control, or as simple registered data through the framework module. The data is said to be point to point because the caller of READ_FIFO_DATA must reference the specific application module intended to be the writer. In addition, the application module intended to be the writer must utilize the WRITE_FIFO_DATA procedure call and reference the specific reader application module in order for data to be transferred. In general, application modules reference one another by VHDL entity name. However, when an application module references itself (when looping back data), that application module must refer to itself as this_module and not by its own entity name.
Multiple Channel Setup
Each application module is allowed to set up any number of point to point channels. To set up multiple read channels, an application module makes multiple calls to READ_FIFO_DATA, each on a different resource index,
(M). Before compile time, each application modules entity name is mapped to as a constant integer value that specifies the starting resource index assigned to that application module. Thus, it is possible to read from two or more data channels intended for an application module simply by adding an offset number to the intended writer application module entity name.
- Note
- The application module that calls READ_FIFO_DATA is the 'owner' the fifo hardware and is responsible for setting up the depth for the fifo buffer using the optional BUFF_SIZE parameter. If the BUFF_SIZE is not specified, the fifo depth is set to the minimum depth of 4 elements in order to conserve resources. This also means that only the application module that calls READ_FIFO_DATA is allowed to reset the fifo buffer by calling RESET_FIFO.
Operation
When the READ_FIFO_DATA procedure call is made, the reader application module waits for the state_reg_rec(M).fifo_data_ready signal to become logic '1' indicating that the fifo is not empty, then reads the state_reg_rec(M).fifo_data_reg register from a framework fifo when the state_reg_rec(M).fifo_data_valid signal becomes logic '1'. Both the state_reg_rec(M).fifo_data_ready and state_reg_rec(M).fifo_data_valid signals are used for flow control and valid data is available on the receive side of the fifo buffer after 3 clock cycles it was sent from the writer.
If no flow control is necessary, registered point to point data can still be sent using the WRITE_FIFO_DATA and received using the READ_FIFO_DATA procedure calls. This data will be always available from the writer application module on the state_reg_rec(M).exchange_reg register 1 clock cycle after it is written regardless if state_reg_rec(M).fifo_data_valid is asserted or not. This allows the READ_FIFO_DATA procedure call to be utilized receive both buffered data (with flow control) and low latency registered data (with no flow control) with the same API calls.
The data width of the state_reg_rec(M).fifo_data_reg and state_reg_rec(M).exchange_reg registers will always be data_width number of bits which is specified the config_file. The reader application module is required to extract the range of bits that it is expecting from a subset of the fifo_data_reg bit range.
In addition, the caller of READ_FIFO_DATA can specify a non-negative NUM_ELEMENTS to write to the fifo buffer, and optionally a non-negative transition_state to schedule a state machine transition to when the number of requested elements have been received. If both NUM_ELEMENTS and transition_state are set to the value -1, then the fifo is configured to be a streaming read fifo.
Usage Example
Writing to and Reading from a Fifo
Example API Call(s):
READ_FIFO_DATA( cordic, srr.fifo_data_ready, -1, no_trans, next_state_rec, state_reg_rec );
Call Data [ 8 parameters (6 mandatory, 2 optional) ]
- Parameters
-
[in] sm_index [1] name/offset index of the receiving application module resource or this_module for loopback [in] FIFO_READ_EN [2] enable signal specifying whether the application module is ready to accept data [in] NUM_ELEMENTS [3] number of elements to be read to the buffer (-1 indicates streaming) [in] transition_state [4] integer state to transition to when NUM_ELEMENTS are transferred (-1 or no_trans to ignore) [out] next_state_rec [5] [in] state_reg_rec [6] [in] BUFF_SIZE [7] read fifo buffer size, minimum (4) when in use otherwise (0) [in] filename [8] (optional) string filename that can be used during simulation to write data into a file
Return Data
- Parameters
-
[in] state_reg_rec(M).fifo_data_reg(NUM_DATAX_BITS -1 downto 0): [1] [std_logic_vector] buffered fifo data returned from the framework
[in] state_reg_rec(M).FIFO_DATA_VALID [2] [std_logic] status signal indicating whether fifo_data_reg is valid [in] state_reg_rec(M).FIFO_DATA_COUNT [3] [integer] number of data that has been written (should not need to be used directly) [in] state_reg_rec(M).FIFO_DATA_READY [4] [std_logic] status signal that indicates whether data is available in the read buffer [in] state_reg_rec(M).FIFO_DATA_DONE [5] [std_logic] status signal (strobe) that indicates when the number of specified elements has been read [in] state_reg_rec(M).exchange_reg(NUM_DATAX_BITS -1 downto 0): [6] [std_logic_vector] registered exchange data returned from the framework
Command Reference
Voice and Hotkey Commands:
- See also
- Read Fifo Data Commands
Command Parameter Mapping
- Parameters
-
[in] sm_index [1] "index <module_integer_name>" [in] FIFO_READ_EN [2] "enable <std_logic>" [in] NUM_ELEMENTS [3] "count <integer>" [in] transition_state [4] "go to [state] (<state>|<integer>)" [out] next_state_rec [5] [in] state_reg_rec [6]
[in] BUFF_SIZE [7] "buffer size <integer>" [in] filename* [8] "log [fifo] (data |file) size <integer>"
Command Return Data
- Parameters
-
[in] state_reg_rec(M).fifo_data_reg(NUM_DATAX_BITS -1 downto 0): [1] [std_logic_vector] "fifo data"
[in] state_reg_rec(M).FIFO_DATA_VALID [2] [std_logic] "data valid" [in] state_reg_rec(M).FIFO_READ_COUNT [3] [integer] "read count" [in] state_reg_rec(M).FIFO_DATA_READY [4] [std_logic] "data ready" [in] state_reg_rec(M).FIFO_DATA_DONE [5] [std_logic] "data (done|strobe)" [in] state_reg_rec(M).exchange_reg(NUM_DATAX_BITS -1 downto 0): [6] [std_logic_vector] "exchange register"
Voice/HotKey Command Sequence
READ_FIFO_DATA( example_module, 10, st_read_Done, next_state_rec, state_reg_rec );
| Voice Command | HotKey Sequence |
|---|---|
| "read fifo data" | rf |
| "read from example module" | index example_module |
| "count 10" | count 10 |
| "goto state read done" | goto read_done |
Notes and Warnings
- Note
- 1) The data type of both the fifo_data_reg and exchange_reg registers are always std_logic_vector(data_width downto 0) regardless of overloaded data type written by the WRITE_FIFO_DATA procedure call.
- 2) Streaming fifos use slightly less framework resources because the fifo does not need to utilize a counter for handling the element count and does not need to schedule a state machine transition.
- 3) Writing data from a fifo into a file is not available in the sandbox.
Procedures | |
| READ_FIFO_DATA( sm_index: in integer FIFO_READ_EN: std_logic NUM_ELEMENTS: integer transition_state: integer signal next_state_rec: out NSR state_reg_rec: in SRR BUFF_SIZE: BUFF_SIZE_INTEGER 4 filename: string " " ) | |
| READ_FIFO_DATA( sm_index: in integer FIFO_READ_EN: std_logic NUM_ELEMENTS: integer transition_state: integer signal next_state_rec: out NSR_ARRAY state_reg_rec: in SRR_ARRAY BUFF_SIZE: BUFF_SIZE_INTEGER 4 filename: string " " ) | |
| 0verloaded for array next_state_rec and state_reg_rec. Overloaded for buff_size and filename. | |