led_blink_example

Config File:

[global]
clk_pin = E3
reset_pin = U9
sys_clk_freq = 100E6
reset_polarity = '1'
data_width = 32
control_width = 32
default_signal_polarity = '0'
default_voltage_standard = 3.3V
pinout_filename = PINOUT.xdc
alias srr is state_reg_rec(0);
alias state_reg : integer is state_reg_rec(0).state_reg;
 
[led_blink]
output led(2) = T8, V9
 

VHDL Code:

library ieee;                                                                 -- version: beta
use ieee.std_logic_1164.all;                                                  -- lic: non-commercial
use ieee.numeric_std.all;                                                     -- user: local
use ieee.std_logic_unsigned.all;
use work.user_defs_pkg.all;
use work.speakhdl_api_pkg.all;
 
--==============================================================================================
entity led_blink is
 
    generic (this_sm              : integer :=  -1);                
    port (
              clk                 : in std_logic;                             -- clock: E3, 100MHz
              reset               : in std_logic;                             -- reset: U9, '1'
              sm_input            : in std_logic_vector(-1 downto 0);         -- num inputs:  0
              sm_output           : out std_logic_vector(1 downto 0);         -- num outputs: 2
              sm_io               : inout std_logic_vector(-1 downto 0);      -- num io:      0
              next_state_rec      : out nsr_array(0 to 0);
              state_reg_rec       : in srr_array(0 to 0)                      -- num rsc:     1
         );
 
end entity led_blink;
--==============================================================================================
 
architecture arch of led_blink is
 
    alias led : std_logic_vector(1 downto 0) is sm_output(1 downto 0);         -- output T8,V9
    alias srr is state_reg_rec(0);                                             -- alias (global)
    alias state_reg : integer is state_reg_rec(0).state_reg;                   -- alias (global)
 
begin
--==============================================================================================
                                                                               -- output signals
    led(0) <= '1' when (srr.counter(0).value > sec(1)) else
              '0';
    led(1) <= '1' when (srr.counter(1).value > ms(500)) else
              '0';
 
--==============================================================================================
                                                                              -- units: ms, '0'
process(state_reg_rec)                                                        -- hotkey only
 
begin                               -- Log Status: OK     
 
    --------------------------------------------------------------------------------------------
    ---------------------------sys_clk 100MHz active resource 0 state -1------------------------
    --------------------------------------------------------------------------------------------
    RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );
    --------------------------------------------------------------------------------------------
    CONFIGURE_COUNTER( 0, sec(2), no_trans, next_state_rec, state_reg_rec );
    CONFIGURE_COUNTER( 1, sec(1), no_trans, next_state_rec, state_reg_rec );
 
end process;
 
end architecture arch;
--==============================================================================================
 

See also

sseg_display_example

uart_loopback_example

vga_controller_example