led_blink_example

Config File:
1[global]
2clk_pin = E3
3reset_pin = U9
4sys_clk_freq = 100E6
5reset_polarity = '1'
6data_width = 32
7control_width = 32
8default_signal_polarity = '0'
9default_voltage_standard = 3.3V
10pinout_filename = PINOUT.xdc
11alias srr is state_reg_rec(0);
12alias state_reg : integer is state_reg_rec(0).state_reg;
13
14[led_blink]
15output led(2) = T8, V9
16
VHDL Code:
1library ieee; -- version: beta
2use ieee.std_logic_1164.all; -- lic: non-commercial
3use ieee.numeric_std.all; -- user: local
4use ieee.std_logic_unsigned.all;
5use work.user_defs_pkg.all;
6use work.speakhdl_api_pkg.all;
7
8--==============================================================================================
9entity led_blink is
10
11 generic (this_sm : integer := -1);
12 port (
13 clk : in std_logic; -- clock: E3, 100MHz
14 reset : in std_logic; -- reset: U9, '1'
15 sm_input : in std_logic_vector(-1 downto 0); -- num inputs: 0
16 sm_output : out std_logic_vector(1 downto 0); -- num outputs: 2
17 sm_io : inout std_logic_vector(-1 downto 0); -- num io: 0
18 next_state_rec : out nsr_array(0 to 0);
19 state_reg_rec : in srr_array(0 to 0) -- num rsc: 1
20 );
21
22end entity led_blink;
23--==============================================================================================
24
25architecture arch of led_blink is
26
27 alias led : std_logic_vector(1 downto 0) is sm_output(1 downto 0); -- output T8,V9
28 alias srr is state_reg_rec(0); -- alias (global)
29 alias state_reg : integer is state_reg_rec(0).state_reg; -- alias (global)
30
31begin
32--==============================================================================================
33 -- output signals
34 led(0) <= '1' when (srr.counter(0).value > sec(1)) else
35 '0';
36 led(1) <= '1' when (srr.counter(1).value > ms(500)) else
37 '0';
38
39--==============================================================================================
40 -- units: ms, '0'
41process(state_reg_rec) -- hotkey only
42
43begin -- Log Status: OK
44
45 --------------------------------------------------------------------------------------------
46 ---------------------------sys_clk 100MHz active resource 0 state -1------------------------
47 --------------------------------------------------------------------------------------------
48 RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );
49 --------------------------------------------------------------------------------------------
50 CONFIGURE_COUNTER( 0, sec(2), no_trans, next_state_rec, state_reg_rec );
51 CONFIGURE_COUNTER( 1, sec(1), no_trans, next_state_rec, state_reg_rec );
52
53end process;
54
55end architecture arch;
56--==============================================================================================
57
See also
sseg_display_example
uart_loopback_example
vga_controller_example