sseg_display_example

Config File:

[global]
clk_pin = E3
reset_pin = U9
sys_clk_freq = 100E6
reset_polarity = '1'
data_width = 32
control_width = 32
default_shared_register_polarity = '0'
default_signal_polarity = '0'
default_voltage_standard = 3.3V
pinout_filename = PINOUT.xdc
command_help = False
voice_enabled = False
default_time_units = ms
alias srr is state_reg_rec(0);
alias state_reg : integer is state_reg_rec(0).state_reg;
 
[sseg_display]
output anode(8) = N6, M6, M3, N5, N2, N4, L1, M1
output sseg(7) = L3, N1, L5, L4, K3, M2, L6
constant sseg_array : std_logic_vector_array := read_array_from_file("sseg_array.dat");
 

VHDL Code:

library ieee;                                                                 -- version: beta
use ieee.std_logic_1164.all;                                                  -- lic: non-commercial
use ieee.numeric_std.all;                                                     -- user: local
use ieee.std_logic_unsigned.all;
use work.user_defs_pkg.all;
use work.speakhdl_api_pkg.all;
 
--==============================================================================================
entity sseg_display is
 
    generic (this_sm              : integer :=  -1);                
    port (
              clk                 : in std_logic;                             -- clock: E3, 100MHz
              reset               : in std_logic;                             -- reset: U9, '1'
              sm_input            : in std_logic_vector(-1 downto 0);         -- num inputs:  0
              sm_output           : out std_logic_vector(14 downto 0);        -- num outputs: 15
              sm_io               : inout std_logic_vector(-1 downto 0);      -- num io:      0
              next_state_rec      : out nsr_array(0 to 0);
              state_reg_rec       : in srr_array(0 to 0)
         );
 
end entity sseg_display;
--==============================================================================================
 
architecture arch of sseg_display is
 
    alias anode : std_logic_vector(7 downto 0) is sm_output(7 downto 0);       -- output N6,M6,..
    alias sseg : std_logic_vector(6 downto 0) is sm_output(14 downto 8);       -- output L3,N1,..
    alias srr is state_reg_rec(0);                                             -- alias (global)
    alias state_reg : integer is state_reg_rec(0).state_reg;                   -- alias (global)
    signal mux_counter_i : integer;
 
    constant sseg_array : std_logic_vector_array :=
                             read_array_from_file("sseg_array.dat");           -- const (local)
 
begin
--==============================================================================================
                                                                               -- output signals
    anode(0) <= '0' when (srr.delay.value = 0) else
                '1';
    anode(1) <= '0' when (srr.delay.value = 1) else
                '1';
    anode(2) <= '0' when (srr.delay.value = 2) else
                '1';
    anode(7 downto 3) <= (others => '1');
 
    sseg(6 downto 0) <= sseg_array(mux_counter_i)(6 downto 0);
 
--==============================================================================================
                                                                               -- local signals
    mux_counter_i <= srr.counter(srr.delay.value + 1).value;
 
--==============================================================================================
                                                                              -- units: ms, '0'
process(state_reg_rec)                                                        -- voice disabled
 
begin                               -- Log Status: OK    
 
    --------------------------------------------------------------------------------------------
    ---------------------------sys_clk 100MHz active resource 0 state -1------------------------
    --------------------------------------------------------------------------------------------
    RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );
    --------------------------------------------------------------------------------------------
    TIME_COUNTER( 3, ms(1), next_state_rec, state_reg_rec );
    CONFIGURE_COUNTER( 0, ms(100), -1, next_state_rec, state_reg_rec );
    CONFIGURE_COUNTER( 1, 10, no_trans, next_state_rec, state_reg_rec, chain );
    CONFIGURE_COUNTER( 2, 10, no_trans, next_state_rec, state_reg_rec, chain );
    CONFIGURE_COUNTER( 3, 10, no_trans, next_state_rec, state_reg_rec, chain );
 
end process;
 
end architecture arch;
--==============================================================================================

Data File of Seven Segment Values:

1000000
1111001
0100100
0110000
0011001
0010010
0000010
1111000
0000000
0011000

See also

led_blink_example

uart_loopback_example

vga_controller_example