uart_loopback_example

Config File:
1[global]
2clk_pin = E3
3reset_pin = U9
4sys_clk_freq = 100E6
5reset_polarity = '1'
6data_width = 32
7control_width = 32
8default_shared_register_polarity = '0'
9default_signal_polarity = '0'
10default_voltage_standard = 3.3V
11pinout_filename = PINOUT.xdc
12command_help = True
13voice_enabled = False
14default_time_units = ms
15alias srr is state_reg_rec(0);
16alias state_reg : integer is state_reg_rec(0).state_reg;
17
18[uart_rx]
19input rxd = C4
20constant baud_rate : integer := us(104);
21constant half_baud_rate : integer := us(52);
22
23[uart_tx]
24output txd = D4
25alias byte_ready is state_reg_rec(0).shared_register(8);
26constant baud_rate : integer := us(104);
27
VHDL Code (Uart Receiver):
1library ieee; -- version: beta
2use ieee.std_logic_1164.all; -- lic: non-commercial
3use ieee.numeric_std.all; -- user: local
4use ieee.std_logic_unsigned.all;
5use work.user_defs_pkg.all;
6use work.speakhdl_api_pkg.all;
7
8--==============================================================================================
9entity uart_rx is
10
11 generic (this_sm : integer := -1);
12 port (
13 clk : in std_logic; -- clock: E3, 100MHz
14 reset : in std_logic; -- reset: U9, '1'
15 sm_input : in std_logic_vector(0 downto 0); -- num inputs: 1
16 sm_output : out std_logic_vector(-1 downto 0); -- num outputs: 0
17 sm_io : inout std_logic_vector(-1 downto 0); -- num io: 0
18 next_state_rec : out nsr_array(0 to 0);
19 state_reg_rec : in srr_array(0 to 0) -- num rsc: 1
20 );
21
22end entity uart_rx;
23--==============================================================================================
24
25architecture arch of uart_rx is
26
27 alias rxd : std_logic is sm_input(0); -- input C4
28 alias srr is state_reg_rec(0); -- alias (global)
29 alias state_reg : integer is state_reg_rec(0).state_reg; -- alias (global)
30 constant st_init : integer := 0;
31 constant st_start : integer := 1;
32 constant st_shift : integer := 2;
33 constant st_done : integer := 3;
34 constant baud_rate : integer := us(104); -- const (local)
35 constant half_baud_rate : integer := us(52); -- const (local)
36
37begin
38--==============================================================================================
39 -- units: ms, '0'
40process(state_reg_rec) -- hotkey only
41
42begin -- Log Status: OK
43
44 --------------------------------------------------------------------------------------------
45 ---------------------------sys_clk 100MHz active resource 0 state -1------------------------
46 --------------------------------------------------------------------------------------------
47 RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );
48 --------------------------------------------------------------------------------------------
49 SHARED_REGISTER( uart_tx, srr.counter(0).done, next_state_rec, state_reg_rec, 8 );
50 CONFIGURE_COUNTER( 0, 1, no_trans, next_state_rec, state_reg_rec, srr.last_state = st_done );
51
52sm0: case (state_reg) is
53 when st_init =>
54 SHARED_REGISTER( uart_tx, srr.shift_left(7 downto 0), next_state_rec, state_reg_rec );
55 CONDITIONAL_TRANSITION( 0, rxd = '0', st_start, next_state_rec, state_reg_rec );
56 when st_start =>
57 TRANSITION( st_shift, 1, half_baud_rate, next_state_rec, state_reg_rec );
58 when st_shift =>
59 SHIFT_DATA_LEFT( rxd, 1, next_state_rec, state_reg_rec, srr.divide.done );
60 TRANSITION( st_done, 8, baud_rate, next_state_rec, state_reg_rec );
61 when st_done =>
62 TRANSITION( st_init, 1, baud_rate, next_state_rec, state_reg_rec );
63 when others =>
64end case;
65
66end process;
67
68end architecture arch;
69--==============================================================================================
70
VHDL Code (Uart Transmitter):
1library ieee; -- version: beta
2use ieee.std_logic_1164.all; -- lic: non-commercial
3use ieee.numeric_std.all; -- user: local
4use ieee.std_logic_unsigned.all;
5use work.user_defs_pkg.all;
6use work.speakhdl_api_pkg.all;
7
8--==============================================================================================
9entity uart_tx is
10
11 generic (this_sm : integer := -1);
12 port (
13 clk : in std_logic; -- clock: E3, 100MHz
14 reset : in std_logic; -- reset: U9, '1'
15 sm_input : in std_logic_vector(-1 downto 0); -- num inputs: 0
16 sm_output : out std_logic_vector(0 downto 0); -- num outputs: 1
17 sm_io : inout std_logic_vector(-1 downto 0); -- num io: 0
18 next_state_rec : out nsr_array(0 to 0);
19 state_reg_rec : in srr_array(0 to 0) -- num rsc: 1
20 );
21
22end entity uart_tx;
23--==============================================================================================
24
25architecture arch of uart_tx is
26
27 alias txd : std_logic is sm_output(0); -- output D4
28 alias byte_ready is state_reg_rec(0).shared_register(8); -- alias (local)
29 alias srr is state_reg_rec(0); -- alias (global)
30 alias state_reg : integer is state_reg_rec(0).state_reg; -- alias (global)
31 constant st_init : integer := 0;
32 constant st_start : integer := 1;
33 constant st_shift : integer := 2;
34 constant st_stop : integer := 3;
35 constant baud_rate : integer := us(104); -- const (local)
36
37begin
38--==============================================================================================
39 -- output signals
40 txd <= '0' when (state_reg = st_start) else
41 srr.shift_right(0) when (state_reg = st_shift) else
42 '1';
43
44--==============================================================================================
45 -- units: ms, '0'
46process(state_reg_rec) -- hotkey only
47
48begin -- Log Status: OK
49
50 --------------------------------------------------------------------------------------------
51 ---------------------------sys_clk 100MHz active resource 0 state -1------------------------
52 --------------------------------------------------------------------------------------------
53 RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );
54 --------------------------------------------------------------------------------------------
55 SHARED_REGISTER( this_sm, read_only, next_state_rec, state_reg_rec );
56
57sm0: case (state_reg) is
58 when st_init =>
59 SHIFT_DATA_RIGHT( srr.shared_register(7 downto 0), reverse_bits, next_state_rec,
60 state_reg_rec );
61 CONDITIONAL_TRANSITION( 0, byte_ready = '1', st_start, next_state_rec, state_reg_rec );
62 when st_start =>
63 TRANSITION( st_shift, 1, baud_rate, next_state_rec, state_reg_rec );
64 when st_shift =>
65 SHIFT_DATA_RIGHT( srr.shared_register(7 downto 0), 1, next_state_rec, state_reg_rec,
66 srr.divide.done );
67 TRANSITION( st_stop, 8, baud_rate, next_state_rec, state_reg_rec );
68 when st_stop =>
69 TRANSITION( st_init, 1, baud_rate, next_state_rec, state_reg_rec );
70 when others =>
71end case;
72
73end process;
74
75end architecture arch;
76--==============================================================================================
77
See also
led_blink_example
sseg_display_example
vga_controller_example