uart_loopback_example

Config File:

[global]
clk_pin = E3
reset_pin = U9
sys_clk_freq = 100E6
reset_polarity = '1'
data_width = 32
control_width = 32
default_shared_register_polarity = '0'
default_signal_polarity = '0'
default_voltage_standard = 3.3V
pinout_filename = PINOUT.xdc
command_help = True
voice_enabled = False
default_time_units = ms
alias srr is state_reg_rec(0);
alias state_reg : integer is state_reg_rec(0).state_reg;
 
[uart_rx]
input rxd = C4
constant baud_rate : integer := us(104);
constant half_baud_rate : integer := us(52);
 
[uart_tx]
output txd = D4
alias byte_ready is state_reg_rec(0).shared_reg(8);
constant baud_rate : integer := us(104);
 

VHDL Code (Uart Receiver):

library ieee;                                                                 -- version: beta
use ieee.std_logic_1164.all;                                                  -- lic: non-commercial
use ieee.numeric_std.all;                                                     -- user: local
use ieee.std_logic_unsigned.all;
use work.user_defs_pkg.all;
use work.speakhdl_api_pkg.all;
 
--==============================================================================================
entity uart_rx is
 
    generic (this_module              : integer :=  -1);
    port (
              clk                 : in std_logic;                             -- clock: E3, 100MHz
              reset               : in std_logic;                             -- reset: U9, '1'
              sm_input            : in std_logic_vector(0 downto 0);          -- num inputs:  1
              sm_output           : out std_logic_vector(-1 downto 0);        -- num outputs: 0
              sm_io               : inout std_logic_vector(-1 downto 0);      -- num io:      0
              next_state_rec      : out nsr_array(0 to 0);
              state_reg_rec       : in srr_array(0 to 0)                      -- num rsc:     1
         );
 
end entity uart_rx;
--==============================================================================================
 
architecture arch of uart_rx is
 
    alias rxd : std_logic is sm_input(0);                                      -- input C4
    alias srr is state_reg_rec(0);                                             -- alias (global)
    alias state_reg : integer is state_reg_rec(0).state_reg;                   -- alias (global)
    constant st_init : integer := 0;
    constant st_start : integer := 1;
    constant st_shift : integer := 2;
    constant st_done : integer := 3;
    constant baud_rate : integer := us(104);                                   -- const (local)
    constant half_baud_rate : integer := us(52);                               -- const (local)
 
begin
--==============================================================================================
                                                                              -- units: ms, '1'
process(state_reg_rec)                                                        -- hotkey only
 
begin                            
 
    --------------------------------------------------------------------------------------------
    ---------------------------sys_clk 100MHz active resource 0 state -1------------------------
    --------------------------------------------------------------------------------------------
    RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );
    --------------------------------------------------------------------------------------------
    WRITE_SHARED_REGISTER( uart_tx, srr.counter(0).done, next_state_rec, state_reg_rec, 8 );
    CONFIGURE_COUNTER( 0, 1, no_trans, next_state_rec, state_reg_rec, srr.last_state = st_done );
 
sm0: case (state_reg) is
    when st_init =>
        WRITE_SHARED_REGISTER( uart_tx, srr.left_shift_reg(7 downto 0), next_state_rec,
                                                                        state_reg_rec );
        CONDITIONAL_TRANSITION( 0, rxd = '0', st_start, next_state_rec, state_reg_rec );
    when st_start =>
        TRANSITION( st_shift, half_baud_rate, next_state_rec, state_reg_rec );
    when st_shift =>
        SHIFT_DATA_LEFT( rxd, 1, next_state_rec, state_reg_rec, srr.state_timer.done );
        TRANSITION( st_done, baud_rate, next_state_rec, state_reg_rec, 8 );
    when st_done =>
        TRANSITION( st_init, baud_rate, next_state_rec, state_reg_rec );
    when others =>
end case;
 
end process;
 
end architecture arch;
--==============================================================================================

VHDL Code (Uart Transmitter):

library ieee;                                                                 -- version: beta
use ieee.std_logic_1164.all;                                                  -- lic: non-commercial
use ieee.numeric_std.all;                                                     -- user: local
use ieee.std_logic_unsigned.all;
use work.user_defs_pkg.all;
use work.speakhdl_api_pkg.all;
 
--==============================================================================================
entity uart_tx is
 
    generic (this_module              : integer :=  -1);
    port (
              clk                 : in std_logic;                             -- clock: E3, 100MHz
              reset               : in std_logic;                             -- reset: U9, '1'
              sm_input            : in std_logic_vector(-1 downto 0);         -- num inputs:  0
              sm_output           : out std_logic_vector(0 downto 0);         -- num outputs: 1
              sm_io               : inout std_logic_vector(-1 downto 0);      -- num io:      0
              next_state_rec      : out nsr_array(0 to 0);
              state_reg_rec       : in srr_array(0 to 0)                      -- num rsc:     1
         );
 
end entity uart_tx;
--==============================================================================================
 
architecture arch of uart_tx is
 
    alias txd : std_logic is sm_output(0);                                     -- output D4
    alias byte_ready is state_reg_rec(0).shared_reg(8);                        -- alias (local)
    alias srr is state_reg_rec(0);                                             -- alias (global)
    alias state_reg : integer is state_reg_rec(0).state_reg;                   -- alias (global)
    constant st_init : integer := 0;
    constant st_start : integer := 1;
    constant st_shift : integer := 2;
    constant st_stop : integer := 3;
    constant baud_rate : integer := us(104);                                   -- const (local)
 
begin
--==============================================================================================
                                                                               -- output signals
    txd <=                    '0' when (state_reg = st_start) else
           srr.right_shift_reg(0) when (state_reg = st_shift) else
                              '1';
 
--==============================================================================================
                                                                              -- units: ms, '1'
process(state_reg_rec)                                                        -- hotkey only
 
begin                            
 
    --------------------------------------------------------------------------------------------
    ---------------------------sys_clk 100MHz active resource 0 state -1------------------------
    --------------------------------------------------------------------------------------------
    RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );
    --------------------------------------------------------------------------------------------
    READ_SHARED_REGISTER( this_module, next_state_rec, state_reg_rec );
 
sm0: case (state_reg) is
    when st_init =>
        SHIFT_DATA_RIGHT( srr.shared_reg(7 downto 0), reverse_bits, next_state_rec, state_reg_rec );
        CONDITIONAL_TRANSITION( 0, byte_ready = '1', st_start, next_state_rec, state_reg_rec );
    when st_start =>
        TRANSITION( st_shift, baud_rate, next_state_rec, state_reg_rec );
    when st_shift =>
        SHIFT_DATA_RIGHT( srr.shared_reg(7 downto 0), 1, next_state_rec, state_reg_rec,
                                                                 srr.state_timer.done );
        TRANSITION( st_stop, baud_rate, next_state_rec, state_reg_rec, 8 );
    when st_stop =>
        TRANSITION( st_init, baud_rate, next_state_rec, state_reg_rec );
    when others =>
end case;
 
end process;
 
end architecture arch;
--==============================================================================================

See also

led_blink_example

sseg_display_example

vga_controller_example