API Description | Functions
COMMUNICATIONS API

Overview

The Communications API implements the capability for application modules to communicate with one another by way of procedure calls. Currently, the Communications API consists of (4) procedures, READ_FIFO_DATA, WRITE_FIFO_DATA, RESET_FIFO and SHARED_REGISTER. The READ_FIFO_DATA and WRITE_FIFO_DATA setup channels for point-to-point data path communication while the SHARED_REGISTER procedure call implements a simple but flexable multipoint control path where multiple application modules read/write control data.

The data widths of both the data path and the control path can be configured independently using the configuration file data_width and control_width parameters. However, in most use cases the two values are made the same.

The procedures are overloaded for data types and support optional parameters in order to provide a high level of flexibility while retaining a consistent call interface.

See also
COUNTER API
EDGE DETECTION API
STATE MACHINE API
SHIFT REGISTER API

API Description

 WRITE_FIFO_DATA
 Procedure to write data to a fifo buffer (or register) for 'data path' communications (overloaded)
 
 READ_FIFO_DATA
 Procedure to read data from a fifo buffer (or register) for 'data path' communications (overloaded)
 
 RESET_FIFO
 Procedure to reset a fifo buffer on a resource clock domain.
 
 SHARED_REGISTER
 Procedure to read/write data to a shared register for 'control path' communications (overloaded)
 

Procedures

  WRITE_FIFO_DATA(
sm_index: in integer
data_in: integer
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR
state_reg_rec: in SRR
)
  WRITE_FIFO_DATA(
sm_index: in integer
data_in: integer
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR_ARRAY
state_reg_rec: in SRR_ARRAY
)
  WRITE_FIFO_DATA(
sm_index: in integer
data_in: INTEGER_ARRAY
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR
state_reg_rec: in SRR
REPEAT_OPTION: REPEAT_OPTION_TYPE ONE_PASS
)
  WRITE_FIFO_DATA(
sm_index: in integer
data_in: INTEGER_ARRAY
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR_ARRAY
state_reg_rec: in SRR_ARRAY
REPEAT_OPTION: REPEAT_OPTION_TYPE ONE_PASS
)
  WRITE_FIFO_DATA(
sm_index: in integer
data_in: std_logic_vector_array
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR
state_reg_rec: in SRR
REPEAT_OPTION: REPEAT_OPTION_TYPE ONE_PASS
)
  WRITE_FIFO_DATA(
sm_index: in integer
data_in: std_logic_vector_array
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR_ARRAY
state_reg_rec: in SRR_ARRAY
REPEAT_OPTION: REPEAT_OPTION_TYPE ONE_PASS
)
  WRITE_FIFO_DATA(
sm_index: in std_logic_vector
data_in: std_logic_vector
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR
state_reg_rec: in SRR
BIT_OPTION: BIT_OPTION_TYPE ZERO_PAD
)
  WRITE_FIFO_DATA(
sm_index: in std_logic_vector
data_in: std_logic_vector
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR_ARRAY
state_reg_rec: in SRR_ARRAY
BIT_OPTION: BIT_OPTION_TYPE ZERO_PAD
)
  WRITE_FIFO_DATA(
sm_index: in std_logic_vector
data_in: integer
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR
state_reg_rec: in SRR
)
  WRITE_FIFO_DATA(
sm_index: in std_logic_vector
data_in: integer
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR_ARRAY
state_reg_rec: in SRR_ARRAY
)
  WRITE_FIFO_DATA(
sm_index: in std_logic_vector
data_in: INTEGER_ARRAY
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR
state_reg_rec: in SRR
REPEAT_OPTION: REPEAT_OPTION_TYPE ONE_PASS
)
  WRITE_FIFO_DATA(
sm_index: in std_logic_vector
data_in: INTEGER_ARRAY
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR_ARRAY
state_reg_rec: in SRR_ARRAY
REPEAT_OPTION: REPEAT_OPTION_TYPE ONE_PASS
)
  WRITE_FIFO_DATA(
sm_index: in std_logic_vector
data_in: std_logic_vector_array
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR
state_reg_rec: in SRR
REPEAT_OPTION: REPEAT_OPTION_TYPE ONE_PASS
)
  WRITE_FIFO_DATA(
sm_index: in std_logic_vector
data_in: std_logic_vector_array
data_valid: in std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR_ARRAY
state_reg_rec: in SRR_ARRAY
REPEAT_OPTION: REPEAT_OPTION_TYPE ONE_PASS
)
  READ_FIFO_DATA(
sm_index: in std_logic_vector
FIFO_READ_EN: std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR
state_reg_rec: in SRR
BUFF_SIZE: BUFF_SIZE_INTEGER 4
filename: string " "
)
  READ_FIFO_DATA(
sm_index: in std_logic_vector
FIFO_READ_EN: std_logic
NUM_ELEMENTS: integer
transition_state: integer
signal next_state_rec: out NSR_ARRAY
state_reg_rec: in SRR_ARRAY
BUFF_SIZE: BUFF_SIZE_INTEGER 4
filename: string " "
)