The RESET_FIFO procedure resets the fifo buffer on a resource domain to its default state. This involves resetting the internal read/write counters, zeroing any element counters that may have been inferred and clearing the fifo_full and fifo_emtpy flags. In order to successfully reset a fifo buffer, the RESET_FIFO procedure call must stay asserted for at least two consecutive clock cycles.
This means the RESET_FIFO procedure call will almost always appear within a state machine state in conjunction with a TRANSITION procedure call that ensures that the state machine is held in that state for at least two clock cycles.

It should be noted that it is the application module that calls READ_FIFO_DATA which actually 'owns' the fifo hardware and is allowed to reset the fifo buffer by calling RESET_FIFO and not the application module that calls WRITE_FIFO_DATA.

Usage Example

Add Example Usage

Example API Call(s):

RESET_FIFO( next_state_rec, state_reg_rec );

Call Data [ 2 parameters (2 mandatory) ]


Return Data

[in]state_reg_rec(M).fifo_data: [1] [std_logic_vector] fifo data with (with flow control)
[in]state_reg_rec(M).datax: [2] [std_logic_vector] registered input data to fifo buffer

Command Reference

Voice and Hotkey Commands:

See also
Reset Fifo Commands

Command Parameter Mapping


Voice/HotKey Command Sequence

RESET_FIFO(next_state_rec, state_reg_rec );

Voice Command HotKey Sequence
"reset fifo" xf

Notes and Warnings

The fifo must be held in reset for at least two clock cycles to reset the internal counter and assert the fifo_empty flag.

See also


  RESET_FIFO( signal next_state_rec: out NSR , state_reg_rec: in SRR )
  RESET_FIFO( signal next_state_rec: out NSR_ARRAY , state_reg_rec: in SRR_ARRAY )
 overloaded for array interface