documentation/app__module__2_8vhd.html

library ieee;                                                                 -- version: beta

use ieee.std_logic_1164.all;                                                  -- lic: non-commercial

use ieee.numeric_std.all;                                                     -- user: guest

use ieee.std_logic_unsigned.all;

use work.user_defs_pkg.all;

use work.speakhdl_api_pkg.all;


--==============================================================================================

entity app_module_2 is


    generic (this_sm              : integer :=  -1);

    port (

              clk                 : in std_logic;                             -- clock: E3, 100MHz

              reset               : in std_logic;                             -- reset: U9, '1'

              sm_input            : in std_logic_vector(5 downto 0);          -- num inputs:  6

              sm_output           : out std_logic_vector(0 downto 0);         -- num outputs: 1

              sm_io               : inout std_logic_vector(7 downto 0);       -- num io:      8

              next_state_rec      : out nsr_array(0 to 0);

              state_reg_rec       : in srr_array(0 to 0)

         );


end entity app_module_2;

--==============================================================================================


architecture arch of app_module_2 is


    alias addr_valid : std_logic is sm_input(0);                               -- input V14

    alias bus_address : std_logic_vector(2 downto 0) is sm_input(3 downto 1);  -- input ..

    alias data_valid : std_logic is sm_input(4);                               -- input U14

    alias data_write : std_logic is sm_input(5);                               -- input V16

    alias data_wait : std_logic is sm_output(0);                               -- output N9

    alias bus_data : std_logic_vector(7 downto 0) is sm_io(7 downto 0);        -- io R14,..

    alias srr is state_reg_rec(0);                                             -- alias (global)

    alias state_reg : integer is state_reg_rec(0).state_reg;                   -- alias (global)


begin

--==============================================================================================

                                                                              -- units: ms, '0'

process(state_reg_rec)                                                        -- hotkey only


begin


    --------------------------------------------------------------------------------------------

    ---------------------------sys_clk 100MHz active resource 0 state -1------------------------

    --------------------------------------------------------------------------------------------

    RESOURCE_SELECT( sys_clk, next_state_rec, state_reg_rec );

    --------------------------------------------------------------------------------------------


end process;


end architecture arch;

--==============================================================================================