TOP.vhd File Reference

Overview

TOP.vhd is one of (4) auto-generated files that SpeakHDL creates or updates inside the top directory when the 'ok' command is given. It represents the top level of a FPGA design. However, when using a flat design architecture, the framework module and all application modules are always located at the top level of the hierarchy. Thus, with SpeakHDL, the top level of a design has much less significance than the top level in a traditional hierarchical architecture. When the 'ok' command is given, SpeakHDL indexes each application module, calculates the total number of I/O signals that are utilized by application modules, then auto-generates the top level design file. This is done by wiring up the next_state_rec and state_reg_rec array signals of each application module to corresponding portion of the framework module next_state_rec_array and state_reg_rec_array indexes.

The strategy is also generalized for the case of multiple framework modules that operate on multiple clock domains. To support multiple clock domains, the TOP.vhd file defines both a clk signal and a clk_vector signal where the clk signal is always the same as the sys_clk which is also equal to clk_vector(0). Higher indexes of the clock_vector signal will only be utilized by a framework module when the FPGA has multiple clock domains.

Example TOP.vhd File

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.user_defs_pkg.all;
use work.speakhdl_api_pkg.all;
entity TOP is
port (
clk : in std_logic;
clk_vector : in std_logic_vector(0 to NUM_CLOCK_DOMAINS -1) := (others => '1');
reset : in std_logic := '0';
TOP_INPUT : in std_logic_vector(HIGH_BIT(INPUT,NUM_RESOURCES-1, FIXED_PORT_WIDTH) downto 0) := (others =>'0');
TOP_OUTPUT : out std_logic_vector(HIGH_BIT(OUTPUT,NUM_RESOURCES-1, FIXED_PORT_WIDTH) downto 0) := (others =>'0');
TOP_IO : inout std_logic_vector(HIGH_BIT(INPUT_OUTPUT,NUM_RESOURCES-1) downto 0)
);
end entity TOP;
architecture arch of TOP is
-------------------------------------------------------------------------------------------------
------------------------------ENTITY CONNECTION SIGNALS------------------------------------------
-------------------------------------------------------------------------------------------------
signal NEXT_STATE_REC_ARRAY_app_module_2 : NSR_ARRAY(0 to 0 );
signal STATE_REG_REC_ARRAY_app_module_2: SRR_ARRAY(0 to 0);
signal NEXT_STATE_REC_ARRAY_app_module_1 : NSR_ARRAY(0 to 0 );
signal STATE_REG_REC_ARRAY_app_module_1: SRR_ARRAY(0 to 0);
-------------------------------------------------------------------------------------------------
------------------------------CLOCK DOMAIN SIGNALS-----------------------------------------------
-------------------------------------------------------------------------------------------------
signal NEXT_STATE_REC_ARRAY_0 : NSR_ARRAY(0 to 1);
signal STATE_REG_REC_ARRAY_0 : SRR_ARRAY(0 to 1);
begin
------------------------------------------------------------------------------------------------
-----------------------------ASSIGNMENT PROCESS-------------------------------------------------
------------------------------------------------------------------------------------------------
app_module_2_assign: process(NEXT_STATE_REC_ARRAY_app_module_2(0 to 0), STATE_REG_REC_ARRAY_0(0 to 0))
begin
NEXT_STATE_REC_ARRAY_0(0 to 0) <= NEXT_STATE_REC_ARRAY_app_module_2(0 to 0);
STATE_REG_REC_ARRAY_app_module_2(0 to 0) <= STATE_REG_REC_ARRAY_0(0 to 0);
end process;
app_module_1_assign: process(NEXT_STATE_REC_ARRAY_app_module_1(0 to 0), STATE_REG_REC_ARRAY_0(1 to 1))
begin
NEXT_STATE_REC_ARRAY_0(1 to 1) <= NEXT_STATE_REC_ARRAY_app_module_1(0 to 0);
STATE_REG_REC_ARRAY_app_module_1(0 to 0) <= STATE_REG_REC_ARRAY_0(1 to 1);
end process;
------------------------------------------------------------------------------------------------
------------------------------INSTANTIATE COMPONENTS--------------------------------------------
------------------------------------------------------------------------------------------------
app_module_2_0: entity work.app_module_2
generic map (app_module_2)
port map (
clk,
reset,
TOP_INPUT(HIGH_BIT(INPUT,app_module_2) downto LOW_BIT(INPUT,app_module_2)),
TOP_OUTPUT(HIGH_BIT(OUTPUT,app_module_2) downto LOW_BIT(OUTPUT,app_module_2)),
TOP_IO(HIGH_BIT(INPUT_OUTPUT,app_module_2) downto LOW_BIT(INPUT_OUTPUT,app_module_2)),
NEXT_STATE_REC_ARRAY_app_module_2(0 to 0),
STATE_REG_REC_ARRAY_app_module_2(0 to 0 )
);
app_module_1_0: entity work.app_module_1
generic map (app_module_1)
port map (
clk,
reset,
TOP_INPUT(HIGH_BIT(INPUT,app_module_1) downto LOW_BIT(INPUT,app_module_1)),
TOP_OUTPUT(HIGH_BIT(OUTPUT,app_module_1) downto LOW_BIT(OUTPUT,app_module_1)),
TOP_IO(HIGH_BIT(INPUT_OUTPUT,app_module_1) downto LOW_BIT(INPUT_OUTPUT,app_module_1)),
NEXT_STATE_REC_ARRAY_app_module_1(0 to 0),
STATE_REG_REC_ARRAY_app_module_1(0 to 0 )
);
------------------------------------------------------------------------------------------------
------------------------------FRAMEWORK---------------------------------------------------------
------------------------------------------------------------------------------------------------
FRAMEWORK_0: entity work.framework
port map (
clk => clk,
reset => reset,
NEXT_STATE_REC_ARRAY =>NEXT_STATE_REC_ARRAY_0,
STATE_REG_REC_ARRAY_BUFF => STATE_REG_REC_ARRAY_0
);
end architecture arch;

Example Multiple Framework Module Instantiation

FRAMEWORK_0: entity work.framework
port map (
clk => clk,
reset => reset,
NEXT_STATE_REC_ARRAY =>NEXT_STATE_REC_ARRAY_0,
STATE_REG_REC_ARRAY_BUFF => STATE_REG_REC_ARRAY_0
);
FRAMEWORK_1: entity work.framework
port map (
clk => clk_vector(1),
reset => reset,
NEXT_STATE_REC_ARRAY =>NEXT_STATE_REC_ARRAY_1,
STATE_REG_REC_ARRAY_BUFF => STATE_REG_REC_ARRAY_1
);
Note
1) Disabled application modules do not get instantiated at the top level of the design.
2) The module index which is defined in USER_DEFS_PKG.vhd is passed to each application module from the top level by a VHDL generic constant.
See also
app_module_1.vhd
app_module_2.vhd
IO_CONFIG.cfg
PINOUT.xdc
USER_DEFS_PKG.vhd
TESTBENCH.vhd
SPEAKHDL_API_PKG.vhd