PINOUT.xdc File Reference

Pinout Constraints File

Overview

PINOUT.xdc is one of (4) auto-generated files that SpeakHDL creates or updates inside the top directory when the 'ok' command is given. When the user gives the 'ok' command, SpeakHDL extracts the system clock frequency, global clock and reset pinout information and each application module's local pinout information from the config file. This information is parsed to create a top level constraints file constraints in the vendor specific format to be used during synthesis. SpeakHDL orders the contents of the constraints file first by mode then by in ascending order of module indexes. This ensures some form of uniqueness on structure of the constraints file and ensures that I\O with the lowest module index will occupy the lowest bits of the generic TOP_INPUT, TOP_OUTPUT, or TOP_IO signal range.

Below is the PINOUT.xdc file that gets generated for app_module_1.vhd and app_module_2.vhd with the the corresponding example configuration file when the 'ok' command is given.

Example PINOUT.xdc File

## Reset signal (reset_polarity = '1')
set_property -dict { PACKAGE_PIN U9   IOSTANDARD LVCMOS33 } [get_ports { reset }];
 
 
## Clock signal
set_property -dict { PACKAGE_PIN E3   IOSTANDARD LVCMOS33 } [get_ports { clk }];
create_clock -add -name sys_clk_pin_100_MHz -period 10.0 -waveform {0 5.0} [get_ports { clk }];
 
 
## -------------------------app_module_2 input-------------------------
set_property  -dict { PACKAGE_PIN V14  IOSTANDARD LVCMOS33 } [get_ports { TOP_INPUT[0] }];   #  0  # addr_valid
set_property  -dict { PACKAGE_PIN X3   IOSTANDARD LVCMOS33 } [get_ports { TOP_INPUT[1] }];   #  1  # bus_address(0)
set_property  -dict { PACKAGE_PIN X2   IOSTANDARD LVCMOS33 } [get_ports { TOP_INPUT[2] }];   #  2  # bus_address(1)
set_property  -dict { PACKAGE_PIN X1   IOSTANDARD LVCMOS33 } [get_ports { TOP_INPUT[3] }];   #  3  # bus_address(2)
set_property  -dict { PACKAGE_PIN U14  IOSTANDARD LVCMOS33 } [get_ports { TOP_INPUT[4] }];   #  4  # data_valid
set_property  -dict { PACKAGE_PIN V16  IOSTANDARD LVCMOS33 } [get_ports { TOP_INPUT[5] }];   #  5  # data_write
 
## -------------------------app_module_1 input-------------------------
set_property  -dict { PACKAGE_PIN H14  IOSTANDARD LVCMOS33 } [get_ports { TOP_INPUT[6] }];   #  6  # some_input_name(0)
set_property  -dict { PACKAGE_PIN B9   IOSTANDARD LVCMOS33 } [get_ports { TOP_INPUT[7] }];   #  7  # some_input_name(1)
 
## -------------------------app_module_2 output-------------------------
set_property  -dict { PACKAGE_PIN N9   IOSTANDARD LVCMOS33 } [get_ports { TOP_OUTPUT[0] }];   #  0  # data_wait
 
## -------------------------app_module_1 output-------------------------
set_property  -dict { PACKAGE_PIN A3   IOSTANDARD LVCMOS33 } [get_ports { TOP_OUTPUT[1] }];   #  1  # some_output_name(0)
set_property  -dict { PACKAGE_PIN R5   IOSTANDARD LVCMOS33 } [get_ports { TOP_OUTPUT[2] }];   #  2  # some_output_name(1)
set_property  -dict { PACKAGE_PIN Q1   IOSTANDARD LVCMOS33 } [get_ports { TOP_OUTPUT[3] }];   #  3  # some_output_name(2)
set_property  -dict { PACKAGE_PIN J3   IOSTANDARD LVCMOS33 } [get_ports { TOP_OUTPUT[4] }];   #  4  # some_output_name(3)
 
## -------------------------app_module_2 io-------------------------
set_property  -dict { PACKAGE_PIN R14  IOSTANDARD LVCMOS33 } [get_ports { TOP_IO[0] }];   #  0  # bus_data(0)
set_property  -dict { PACKAGE_PIN R13  IOSTANDARD LVCMOS33 } [get_ports { TOP_IO[1] }];   #  1  # bus_data(1)
set_property  -dict { PACKAGE_PIN P13  IOSTANDARD LVCMOS33 } [get_ports { TOP_IO[2] }];   #  2  # bus_data(2)
set_property  -dict { PACKAGE_PIN T12  IOSTANDARD LVCMOS33 } [get_ports { TOP_IO[3] }];   #  3  # bus_data(3)
set_property  -dict { PACKAGE_PIN N11  IOSTANDARD LVCMOS33 } [get_ports { TOP_IO[4] }];   #  4  # bus_data(4)
set_property  -dict { PACKAGE_PIN R11  IOSTANDARD LVCMOS33 } [get_ports { TOP_IO[5] }];   #  5  # bus_data(5)
set_property  -dict { PACKAGE_PIN P10  IOSTANDARD LVCMOS33 } [get_ports { TOP_IO[6] }];   #  6  # bus_data(6)
set_property  -dict { PACKAGE_PIN R10  IOSTANDARD LVCMOS33 } [get_ports { TOP_IO[7] }];   #  7  # bus_data(7)
 

Note

Comments are added to the .xdc file that map user specified aliased I/O signal names to the generic TOP_INPUT, TOP_OUTPUT or TOP_IO signal names appearing in the top level file.

See also

IO_CONFIG.cfg

USER_DEFS_PKG.vhd

TOP.vhd

TESTBENCH.vhd

SPEAKHDL_API_PKG.vhd