TESTBENCH.vhd File Reference

Overview

TESTBENCH.vhd is one of (4) auto-generated files that SpeakHDL creates or updates inside the top directory when the 'ok' command is given. The TESTBENCH.vhd instantiates the top level design file, drives the clock vector and sets the reset signal to it's non-asserted state. Despite its name, testbench development with SpeakHDL is not developed in the same manner as a traditional testbench. With SpeakHDL, test stimulus is intend to be driven from one application module to another by using a fifo or a shared register.

Example Testbench File

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.user_defs_pkg.all;
use work.speakhdl_api_pkg.all;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
entity testbench is
end entity testbench;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
architecture arch of testbench is
signal clk : std_logic := '1';
signal clk_vector : std_logic_vector(0 to NUM_CLOCK_DOMAINS -1) := (others => '1');
signal reset : std_logic := not(RESET_POLARITY); --default framework not in reset
-------------------------------------test port------------------------------------------
constant period : time := 1 sec / SYS_CLK;
begin
------------------------------------------------------------------------------
-----------------------------UUT instantiation--------------------------------
top: entity work.TOP
port map( clk =>clk,
clk_vector =>clk_vector,
reset =>reset
);
------------------------------------------------------------------------------
----------------------------tb_clk and reset-----------------------------------
clk <= not clk after period/2;
--reset <= '0';
--reset <= not reset after 40 us;
CLK_GEN: for i in 0 to NUM_CLOCK_DOMAINS -1 generate
constant period : time := 1 sec / SM_CLOCK_ARRAY(i);
begin
clk_vector(i) <= not clk_vector(i) after period/2;
end generate;
end architecture arch;
See also
USER_DEFS_PKG.vhd
TOP.vhd
PINOUT.xdc
IO_CONFIG.cfg
SPEAKHDL_API_PKG.vhd