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VGA Controller Example

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Design Objective(s):

Design A 640x480 VGA controller to display red and green vertical stripes on a monitor.
Understand different ways to designate a signal to be an I/O signal that is bound for FPGA pins vs a local signal that is to be used internally.

Show Hotkey Command Sequence

Top Level Design Structure

Design Discussion

Configuring FPGA logic to act as a simple VGA controller is straight forward. All that is needed is two general purpose counters to be used for controlling the horizontal and vertical sync signal timing. Because the VGA controller outputs analog video to the display while the FPGA has a a digital output, resistors on the development board are used convert 4 digital output pins from the FPGA to a single analog video signal for each of the 3 RGB pins on the VGA connector. To display vertical stripes on the screen from the FPGA, we alternate between driving all 4 bits of the red signal to logic 1 while the green signal is driven to logic 0, then drive all 4 bits of the green signal to logic 1 while driving the red to logic 0. Because the blue color is not utilized, all 4 bits of the blue signal are always driven to logic 0.

The design also shows three ways one can specify a signal to be treated as an I/O pin with SpeakHDL. The first way is by creating a local signal then using the 'pin' command to assign location constraints to the signal. That method is used to assign the red and green signals as outputs. Another method of assigning output signals is by using the output or input command before declaring the signal then immediately specifying the pin locations. This method is utilized for declaring the h_sync, and v_sync signals to be outputs. Both of these commands are used to make an entry into the IO_CONFIG.cfg file. The third way to designate an IO signal as is by editing the pinout information directly in the config file. This method was done when assigning the clk_pin and reset_pin locations.

In order to synthesize the design, SpeakHDL requires a clk_pin location to be mapped to a clock oscillator on the development board and reset_pin location which can be mapped to any input pin location (button or switch, ect). Before any clock and reset location have been specified, SpeakHDL sets the default pin locations to be '<>' and prints these locations as VHDL comments next to the port interface of each application module.

When either the clock or reset pin locations are not specified, SpeakHDL will generate at least one error when the 'ok' command is given.

Details for the errors and warnings can be viewed in the ok.log file. After pin location information for the clock and reset pin are given, SpeakHDL will show an ok status.

Hotkey Commands

Select a local directory location for output files *

clear .vhd file and rename application module 'vga_controller'

restart
rename vga_controller.vhd

configure default value for 'else' statement

default 1

setup horizontal counter

time us
cc
count 32.0
h_enable;
0 when counter0 < 5.76
0 when counter0 > 31.36
h_sync;
0 when counter0 < 5.12us

setup vertical counter

time ms
cc1
count 16.672
v_enable;
0 when counter1 < 0.992
0 when counter1 > 16.352
v_sync;
0 when counter1 < 0.064

setup video enable control signal

video_on;
1 when h_enable = 1
and v_enable = 1
else 0

configure output red and green signals

red3:
pin = A3, B4, C5, A4
0 when video_on = 0
1 when counter1 bit 6 = 1
else 0
green3:
pin = C6, A5, B6, A6
0 when video_on = 0
1 when counter1 bit 6 = 0
else 0

drive the blue signal to logic 0 because the color is not in use

blue3:
output blue = B7,C7,D7,D8
0

declare sync and v_sync as output signals

output h_sync = B11
output v_sync = B12
ok

Pin locations must be changed for user specific development board

Writing to a local directory is supported with Chrome and Microsoft Edge browsers

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Entry Into Editor

Open the IO_CONFIG.cfg file in the editor and update the following parameters to match the user specific the development board. Then return to the .vhd file and give the 'ok' command.

IO_CONFIG.cfg

[global]
clk_pin = E3
reset_pin = U9
sys_clk_freq = 100E6
reset_polarity = '1'
...

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