Command Reference

Command Reference

  REFERENCE
  VOICE COMMAND HOTKEY DESCRIPTION
    FILE OPERATIONS API  
  restart from scratch
ok
-
-
-
-
enable (file|<module_integer_name>)
disable (file|<module_integer_name>)
enable all files
disable other files
(enable|disable) voice		 restart
ok
(new|create)  (<module_name>.vhd |< datafile_name>.dat)
(rename| mv)  <module_name>.vhd
(remove|rm) (<module_name>.vhd | <datafile_name>.dat)
(zip|tar) <filename>
enable file [<module_name>]
disable file [<module_name>]
enable all
disable other
(enable|disable) voice		 restart application module
runs parser and updates 'top' level files
creates a new application module or data file
renames the currently focused .vhd file
removes the named application module or data file
creates a zip or tar file of the project directory
enable focus file or .vhd file named
disables focus file or .vhd file named
enables all application modules
disables all other application modules
enables or disables voice input**
       
       
    TEXT EDITOR API  
  remove edit
undo edit
redo edit
--
--
 (remove|rm) [edit]
escape + up
escape + down
F2 + up
F2 + down

 remove selected procedure call or signal assignment
undo (implemented as buffer rotation)
redo (implemented as buffer rotation)
last hotkey command (buffer rotation)
next hotkey command (buffer rotation)
       
       
    CONFIG FILE OPERATIONS API  
  Configuration File Documentation  
  [system] clock [frequency]<integer>([E<integer>]|MHz|kHz)*
clock pin (location | equal)  <location>
reset pin (location | equal)  <location>
reset polarity <(zero|one)>
default [signal] [polarity]
[default] time [units] <(ms|us|s)*>
command help
-
-
-
-		 set clock  = <integer>([E<integer>]|M[Hz]|k[Hz])
set clk_pin =<location>
set reset_pin = <location>
set reset_pol[arity] = <(0|1)>
set default[_signal_polarity] [=] <(0|1)>
set [default_]time[_units] [=] <(ms|us|s)>
set [command] help
set pin=[<pin_location>]
set input <signal_name> [(<integer>)][= <pin_location>]
output <signal_name> [(<integer>)][= <pin_location>]
io_signal_<name> [(<integer>)][= <pin_location>]
 sets the sys_clk frequeny
sets the sys_clk pin location
sets the reset pin loction
sets the reset polarity
sets the default value for else statements when created
sets the time function for integer with a decimal point
toggles the command_help on or off
adds a pin location (or list) to a selected signal
creates an input signal with  a pin location
creates or designates an output signal with pin location
creates or designates an io signal with a pin location
       
       
    ALIASES AND CONSTANTS  
  Aliases and Constants Documentation  
  --
--
--
--
--
 <identifier> is <framework_signal>
<identifier> is (<integer>|<timing_function>)
<identifier> is '(0|1)'
<identifier> is "(0|1)+"
<identifier> is <filename>.dat

 declares a vhdl alias for a framework signal
declares a vhdl constant integer value or  timing function
declares a vhdl constant std_logic value
declares a vhdl constant std_logic_vector value
declares a vhdl std_logic_vector_array read from <fileneame>.dat
       
       
    SIGNAL CONSTRUCTION API  
  Signal Assignments Documentation  
  <signal_name> <signal_name>;
<signal_name>_i
<signal_name><integer>
<signal_name><integer>:[<integer>]		 creates or selects std_logic signal
creates or selects integer signal
creates or selects indexed std_logic_vector
creates or selectes std_logic_vector
  assign <variable> [when <boolean_expression>][else <variable>]
when <boolean_expression>
when (<integer>|<state>)
else <variable>
register
(and | or) <boolean_expression> [else <variable>]
move to [the] top
clear assignments		 assign <variable> [when <boolean_expression>][else <variable>]
when <boolean_expression>
when (<integer>|<state>)
(else <variable>|0|1|<integer>)
register
(and | or) <boolean_expression> [else <variable>]
top
clear[assignments]		 signal assignment
conditional boolean expression for assignment
shorthand boolean expression for assignment
else logic
command indicating whether signal is registered
concatenates an "and" or "or" boolean expresion
forces last when else expression to be the first one
removes all when else expressions from signal
       
       
    COMMUNICATION API (4)  
  Read Fifo Data Documentation  
  read fifo data [<resource_index>] (re|rf)[<integer>] create or select READ_FIFO_DATA 
  index  <module_name>
enable <std_logic>
count (<integer>|<time>)
go to (<integer>|<state>)
buffer [size] <integer>*
axi <component_declaration>[<integer>]
log file [kill]
remove log file		 (index|module)<module_name>
enable <std_logic>
count <integer>
goto (<integer |<state>)
buff <integer>*
axi <component_declaration>[<integer>]
log
(remove|rm) log		 module name enumeration to read data from
read enable std_logic signal
integer number of elements to read before a transition
transition state when number of elements has been read
integer buffer size
--
--
--
  Write Fifo Data Documentation  
  write fifo data [<resource_index>] (wf|wr)[<integer>] create or select WRITE_FIFO_DATA 
  index <module_name>
data <fifo_input_data>
enable <std_logic>
count (<integer>|<time>)
go to (<integer>|<state>)
option (sign_extend | int_file| default)*
axi <component_declaration>[<integer>]
file <filename>
[integer] test_array		 index <module_name>
data (<std_logic_vector>|<integer>)
enable <std_logic>
count <integer>
goto (<integer> | <state>)
[option] (sign_extend | int_file | default)*
axi <component_declaration>[<integer>]
file <filename>
[integer] test_array		 module name enumeration to write data to
input std_logic_vector data to write
write enable std_logic signal
integer number of elements to be written
transition state when number of elements have been written
optional enumeration to sign_extend
--
--
--
  Shared Register Documentation  
  shared register [<resource_index>] sr[<integer>] create or select SHARED_REGISTER 
  index <module_name>
data <std_logic_vector>
data read_only
offset <integer>*		 index <module_name>
data <std_logic_vector>
[data] read_only
offset <integer>*		 module name enumeration
read/write std_logic_vector data
enumeration indicating whether register is read only
number of bits to shift input data to the left
  Reset Fifo Documentation  
  reset fifo [<resource_index>] xf[<integer>] create or select RESET_FIFO procedure call
       
       
       
    COUNTER API (3/4)*  
  Configure Counter Documentation  
  configure counter <array_index> cc[<integer>] create or selcect CONFIGURE_COUNTER
  index <integer>
count (<integer>|<time>)
go to (<integer>|<state>)
enable [when] (<std_logic>|<boolean_expression>)*
enable (<integer>|<state>),  (<integer>|<state>)*
option chain*		 index <integer>
count (<integer>|<time>)
goto (<integer>|<state>)
enable (<std_logic>|<boolean_expression> )*
enable (<integer>|<state>),  (<integer>|<state>)*
[option] chain*		 api call index
terminal count (+1) for counter
transition count when counter reaches terminal count -1
enable std_logic_signal or boolean expression
enable 'tuple' of last state, current state
enumeration indicating on whether to chain counter with previous index
  Reset Counter Documentation  
  reset counter [array_index>] rc[<integer>] reset counter back to zero
  index <integer>
[index] all_counters		 index <integer>
[index] all_counters		 api call index
enumeration indicating to reset all counters
  Time Counter Documentation  
  time counter [<resource_index>] tc[<integer>] create or select TIME_COUNTER
  (delay [count] | count) (<integer>|<time>)
divide [count] (<integer>|<time>)
enable (<std_logic>|<boolean_expression>)		 (delay|count) (<integer>|<time>)
divide (<integer>|<time>)
enable (<std_logic>|<boolean_expression>)		 delay counter terminal count (+1)
divide counter terminal count (+1)
enable std_logic signal or boolean expression
       
       
    STATEMACHINE API (4)  
  Conditional Transition Documentation  
  conditional transition [(<array_index>|<transition_integer>)] ct[<integer>] create or selcect CONDITIONAL_TRANSITION
  index <integer>
[enable] when  <boolean_expression>
go to (<integer>|<state>)
--
(option| trigger [time]) <time>		 index <integer>
when <boolean_expression>
goto (<integer>|<state>)
when <std_logic>
[(option | trigger)] <time>		 api call index
boolean expression
transition state when boolen expression evaluates to true

optional simulation time to force boolean expression to evaluate to true
  Fire Event Documentation  
  fire event <array_index> fire[<integer>] create or select FIRE_EVENT 
  index <integer>
go to (<integer>|<state>)		 index <integer>
goto (<integer>|<state>)		 api call index
transition state when event is confirmed as received
  Register For Event Documentation  
  register for event <array_index> reg[<integer>] create or select REGISTER_FOR _EVENT 
  index <integer>
go to (<integer>|<state>)
trigger [time] <time>*		 index <integer>
goto (<integer>|<state>)
trigger <time>*		 api call index
transition state when event is received by any registration
optional simulation time to raise own event
  Transistion Documentation  
  transition [<transition_integer>] tr[<integer>] create or select TRANSITION 
  go to (<integer>|<state>)
(delay [count] | count) (<integer>|<time>)
divide [count] (<integer>|<time>)		 goto (<integer> | <state>)
(delay|count) (<integer>|<time>)
divide (<integer>|<time>)		 transition state when delay and divide counter values have been reached
delay counter terminal count (+1)
divide counter terminal count (+1)
       
       
    STATEMACHINE CONSTRUCTION API  
  State Machine Construction Documentation  
  configure state machine [<resource_index>]
state (<integer>| <state_name>)
remove state machine [<resource_index>]		 sm[<integer>]
(state|st) (<integer>|<state_name>)
(remove|rm) sm[<integer>]		 create or select state machine
create or select state machine state
remove state machine instancecreate or select state machine
create or select state machine state
remove state machine instance
  (add | insert) <integer> [states]
make <integer> [states]
next state
last state		 (add | insert) <integer>
make <integer>
(next | n)
(last | previous | l | n)		 integer number of states to add to state machine
makes the state machine contain specific number of states
select next state
select previous state
  -- name = <string>[, <string>, <string>...] name or rename states with user defined list of names
       
       
    EDGE DETECTION API (2)  
  Monitor Falling Edges Documentation  
  monitor falling [edges] <array_index> mf[e][<integer>] create or select MONITOR_FALLING_EDGES
  index <integer>
go to (<integer>|<state>)
data <std_logic>		 index <integer>
goto (<integer> |<state>)
data <std_logic>		 api call index
transition state when falling edge is detected
input std_logic signal to monitior for falling edge
  Monitor Risisng Edges Documentation  
  monitor rising [edges] <array_index> mr[e][<integer>] create or select MONITOR_RISING_EDGES 
  index <integer>
go to (<integer>|<state>)
data <std_logic>		 index <integer>
goto (<integer> |<state>)
data <std_logic>		 api call index
transition state when rising edge is detected
input std_logic signal to monitior for rising edge
       
       
    SHIFT REGISTER API (4)  
  Reset Left Shifter Documentation  
  reset [left] shifter [<resource_index>] xl[<integer>] create or select RESET_LEFT_SHIFTER 
       
  Reset Right Shifter Documentation  
  reset right shifter [<resource_index>] xr[<integer>] create or select RESET_RIGHT_SHIFTER
       
  Shift Data Left Documentation  
  shift data left sdl create or select  SHIFT_DATA_LEFT
  data <std_logic_vector>
shift <integer>
enable <std_logic>*
option (sign_extend|rotate|default)*		 data <std_logic_vector>
shift <integer>
enable <std_logic>*
[option] (sign_extend |rotate|default)*		 input data to be shifted to the left
number of bits to shift input data
enabl std_logic signal for shifter
optional enumeration to sign_extend or rotate
  Shift Data Right Documentation  
  shift data right sdr create or select  SHIFT_DATA_RIGHT
  data <std_logic_vector>
shift <integer>
enable <std_logic>*
option (sign_extend|rotate|default)*		 data <std_logic_vector>
shift <integer>
enable <std_logic>*
[option] (sign_extend |rotate|default)*		 input data to be shifted to the right
number of bits to shift input data
enabl std_logic signal for shifter
optional enumeration to sign_extend or rotate
       
       
    COMPONENT CONSTRUCTION API  
  Component Instantiation Documentation  
  add [component] <component_name>
remove [component]  <component_name> [<array_index>]		 add <component_name>
(remove|rm) <component_name>_<index>		 create new component instance
remove component instance
       
       
       
    HELPER API (2)  
  Disable File Documentation  
  disable file
disable (all|other) files		 disable file
disable (all|other)		 create DISABLE_FILE procedure call
disable all other files except current file
       
  Resource Select Documentation  
  resource select [<resource_index>] rs[<integer>] create or select RESOURCE_SELECT procedure call
  clock (sys_clock |<clock_frequency>) clock (sys_clock |<clock_frequency>) clock domain clock frequency in Hz
       
  AXI Stream Interface Documentation  
    PRODUCTIVITY API  
  "loopback[(data|<module_name>)]"
axi <component_name>[<array_index>][<channel_name>]		 loopback[(data|<module_name>)]
axi <component_name>[<array_index>][<channel_name>]		 creates both READ_FIFO_DATA and WRITE_FIFO data calls
conntects framework fifo to axi stream port channels
       
       
  REFERENCE   EXAMPLE  
  VOICE COMMAND HOTKEY DESCRIPTION   VOICE COMMAND HOTKEY  
    FILE OPERATIONS API          
  restart from scratch
ok
-
-
-
-
enable (file|<module_integer_name>)
disable (file|<module_integer_name>)
enable all files
disable other files
(enable|disable) voice		 restart
ok
(new|create)  (<module_name>.vhd |< datafile_name>.dat)
(rename| mv)  <module_name>.vhd
(remove|rm) (<module_name>.vhd | <datafile_name>.dat)
(zip|tar) <filename>
enable file [<module_name>]
disable file [<module_name>]
enable all
disable other
(enable|disable) voice		 restart application module
runs parser and updates 'top' level files
creates a new application module or data file
renames the currently focused .vhd file
removes the named application module or data file
creates a zip or tar file of the project directory
enable focus file or .vhd file named
disables focus file or .vhd file named
enables all application modules
disables all other application modules
enables or disables voice input**		   "restart from scractch"
"ok"
-
-
-
-
"enable file"
"disable file"
"enable all files"
"disable other files"
"disable voice"		 restart
ok
create led_blink.vhd
rename control_module.vhd
remove data_array.dat
zip  source
enable file
disable file
enable all
disable other
disable voice		  
               
               
    TEXT EDITOR API          
  remove edit
undo edit
redo edit
--
--
 (remove|rm) [edit]
escape + up
escape + down
F2 + up
F2 + down

 remove selected procedure call or signal assignment
undo (implemented as buffer rotation)
redo (implemented as buffer rotation)
last hotkey command (buffer rotation)
next hotkey command (buffer rotation)

   "remove edit"
"undo edit"
"redo edit"
--
--


 (remove|rm)
escape + up
escape + down
F2 +  up
F2 + down

  
               
               
    CONFIG FILE OPERATIONS API          
  Configuration File Documentation        
  [system] clock [frequency]<integer>([E<integer>]|MHz|kHz)*
clock pin (location | equal)  <location>
reset pin (location | equal)  <location>
reset polarity <(zero|one)>
default [signal] [polarity]
[default] time [units] <(ms|us|s)*>
command help
-
-
-
-		 set clock  = <integer>([E<integer>]|M[Hz]|k[Hz])
set clk_pin =<location>
set reset_pin = <location>
set reset_pol[arity] = <(0|1)>
set default[_signal_polarity] [=] <(0|1)>
set [default_]time[_units] [=] <(ms|us|s)>
set [command] help
set pin=[<pin_location>]
set input <signal_name> [(<integer>)][= <pin_location>]
output <signal_name> [(<integer>)][= <pin_location>]
io_signal_<name> [(<integer>)][= <pin_location>]
 sets the sys_clk frequeny
sets the sys_clk pin location
sets the reset pin loction
sets the reset polarity
sets the default value for else statements when created
sets the time function for integer with a decimal point
toggles the command_help on or off
adds a pin location (or list) to a selected signal
creates an input signal with  a pin location
creates or designates an output signal with pin location
creates or designates an io signal with a pin location
   "clock one hundred twenty mega-Hertz"
"clock pin location E3"
"reset pin location U9"
"reset polarity one"
"default zero"
"time milli-seconds"
"command help"
-
-
-
-
 clock 120m
clk_pin = E3
reset_pin = U9
reset_pol = 1
default  0
time ms
help
pin = A3, GR2, A3, YY9
input button  = B3
ouput led(3) = G4, C6, D3
io ram_data =  A3, GR2, A3, YY9
  
               
               
    ALIASES AND CONSTANTS          
  Aliases and Constants Documentation        
  --
--
--
--
--
 <identifier> is <framework_signal>
<identifier> is (<integer>|<timing_function>)
<identifier> is '(0|1)'
<identifier> is "(0|1)+"
<identifier> is <filename>.dat

 declares a vhdl alias for a framework signal
declares a vhdl constant integer value or  timing function
declares a vhdl constant std_logic value
declares a vhdl constant std_logic_vector value
declares a vhdl std_logic_vector_array read from <fileneame>.dat		   --
--
--
--
--
 enable_bit is shared_register(8)
baud_rate is 24us
power_detect is '1'
spi_id is "1001001"
data_array is input_data.dat		  
               
               
    SIGNAL CONSTRUCTION API          
  Signal Assignments Documentation     lcd_data(2 downto 0)     <=  (others => '1') when (state_reg = 1) else
                                                "101" when (state_reg = 3) and risign_edge(clk);		  
  <signal_name> <signal_name>;
<signal_name>_i
<signal_name><integer>
<signal_name><integer>:[<integer>]		 creates or selects std_logic signal
creates or selects integer signal
creates or selects indexed std_logic_vector
creates or selectes std_logic_vector		   "lcd data two downto zero"    
  assign <variable> [when <boolean_expression>][else <variable>]
when <boolean_expression>
when (<integer>|<state>)
else <variable>
register
(and | or) <boolean_expression> [else <variable>]
move to [the] top
clear assignments		 assign <variable> [when <boolean_expression>][else <variable>]
when <boolean_expression>
when (<integer>|<state>)
(else <variable>|0|1|<integer>)
register
(and | or) <boolean_expression> [else <variable>]
top
clear[assignments]		 signal assignment
conditional boolean expression for assignment
shorthand boolean expression for assignment
else logic
command indicating whether signal is registered
concatenates an "and" or "or" boolean expresion
forces last when else expression to be the first one
removes all when else expressions from signal

   "assign one when state reg equal one"
"else one zero one when state reg equal to three"
"register"
"else one"
"and switch equal zero"
"move to the top"
"clear assigments"
 1 when 1
101 when 3

register
else 1
and switch = 0
top
clear		  
               
               
    COMMUNICATION API (4)          
  Read Fifo Data Documentation     READ_FIFO_DATA( fft_module,fft_data_valid, 128, 4, next_state_rec(1), state_reg_rec (1));  
  read fifo data [<resource_index>] (re|rf)[<integer>] create or select READ_FIFO_DATA    "read fifo data one" rf1  
  index  <module_name>
enable <std_logic>
count (<integer>|<time>)
go to (<integer>|<state>)
buffer [size] <integer>*
axi <component_declaration>[<integer>]
log file [kill]
remove log file		 (index|module)<module_name>
enable <std_logic>
count <integer>
goto (<integer |<state>)
buff <integer>*
axi <component_declaration>[<integer>]
log
(remove|rm) log		 module name enumeration to read data from
read enable std_logic signal
integer number of elements to read before a transition
transition state when number of elements has been read
integer buffer size
--
--
--		   "read from fft module"
"enable fft data valid"
"count one twenty eight"
"go to state four"		 index fft_module
enable fft_valid
count 128
goto 4		  
  Write Fifo Data Documentation     WRITE_FIFO_DATA( syncronizer, sync_data(23 downto 0), '1', -1, -1, next_state_rec, state_reg_rec );  
  write fifo data [<resource_index>] (wf|wr)[<integer>] create or select WRITE_FIFO_DATA    "write fifo data" wr  
  index <module_name>
data <fifo_input_data>
enable <std_logic>
count (<integer>|<time>)
go to (<integer>|<state>)
option (sign_extend | int_file| default)*
axi <component_declaration>[<integer>]
file <filename>
[integer] test_array		 index <module_name>
data (<std_logic_vector>|<integer>)
enable <std_logic>
count <integer>
goto (<integer> | <state>)
[option] (sign_extend | int_file | default)*
axi <component_declaration>[<integer>]
file <filename>
[integer] test_array		 module name enumeration to write data to
input std_logic_vector data to write
write enable std_logic signal
integer number of elements to be written
transition state when number of elements have been written
optional enumeration to sign_extend
--
--
--		   "write to syncrhonizer"
"data sync_data threefour down to zero"
"enable one"		 index synchronizer
data sync_data23:0
enable 1		  
  Shared Register Documentation     SHARED_REGISTER( fft_module, read_only, next_state_rec, state_reg_rec, 16 )  
  shared register [<resource_index>] sr[<integer>] create or select SHARED_REGISTER    "shared register" sr  
  index <module_name>
data <std_logic_vector>
data read_only
offset <integer>*		 index <module_name>
data <std_logic_vector>
[data] read_only
offset <integer>*		 module name enumeration
read/write std_logic_vector data
enumeration indicating whether register is read only
number of bits to shift input data to the left		   "index fft module"
"data read_only"
"offset sixteen"		 index fft_module
data read_only
offset 16		  
  Reset Fifo Documentation     RESET_FIFO( next_state_rec, state_reg_rec );  
  reset fifo [<resource_index>] xf[<integer>] create or select RESET_FIFO procedure call   "reset fifo" xf  
               
               
               
    COUNTER API (3/4)*          
  Configure Counter Documentation     CONFIGURE_COUNTER( 1, 1024, 3, next_state_rec, state_reg_rec, chain );  
  configure counter <array_index> cc[<integer>] create or selcect CONFIGURE_COUNTER   "configure counter one" cc1  
  index <integer>
count (<integer>|<time>)
go to (<integer>|<state>)
enable [when] (<std_logic>|<boolean_expression>)*
enable (<integer>|<state>),  (<integer>|<state>)*
option chain*		 index <integer>
count (<integer>|<time>)
goto (<integer>|<state>)
enable (<std_logic>|<boolean_expression> )*
enable (<integer>|<state>),  (<integer>|<state>)*
[option] chain*		 api call index
terminal count (+1) for counter
transition count when counter reaches terminal count -1
enable std_logic_signal or boolean expression
enable 'tuple' of last state, current state
enumeration indicating on whether to chain counter with previous index		   "count ten twenty four"
"go to state three"
"enable chain"		 cc1
count 1024
goto 3
enable chain		  
  Reset Counter Documentation     RESET_COUNTER( all_counters, next_state_rec, state_reg_rec );  
  reset counter [array_index>] rc[<integer>] reset counter back to zero   "reset counter" rc1  
  index <integer>
[index] all_counters		 index <integer>
[index] all_counters		 api call index
enumeration indicating to reset all counters		   "all counters" all_counters  
  Time Counter Documentation     TIME_COUNTER( 1, us(2.2), next_state_rec, state_reg_rec );  
  time counter [<resource_index>] tc[<integer>] create or select TIME_COUNTER   "time counter" tc  
  (delay [count] | count) (<integer>|<time>)
divide [count] (<integer>|<time>)
enable (<std_logic>|<boolean_expression>)		 (delay|count) (<integer>|<time>)
divide (<integer>|<time>)
enable (<std_logic>|<boolean_expression>)		 delay counter terminal count (+1)
divide counter terminal count (+1)
enable std_logic signal or boolean expression		   "delay 5"
"divide two point two milli-seconds"		 delay 5
divide 2.2ms		  
               
               
    STATEMACHINE API (4)          
  Conditional Transition Documentation     CONDITIONAL_TRANSITION( 0, control_vector(1) = '1', st_wait, next_state_rec, state_reg_rec );  
  conditional transition [(<array_index>|<transition_integer>)] ct[<integer>] create or selcect CONDITIONAL_TRANSITION   "conditional transition zero" ct  
  index <integer>
[enable] when  <boolean_expression>
go to (<integer>|<state>)
--
(option| trigger [time]) <time>		 index <integer>
when <boolean_expression>
goto (<integer>|<state>)
when <std_logic>
[(option | trigger)] <time>		 api call index
boolean expression
transition state when boolen expression evaluates to true

optional simulation time to force boolean expression to evaluate to true		   "when control_pin one equal one"
"goto state wait"		 when control_pin(1) = 1
goto wait		  
  Fire Event Documentation     FIRE_EVENT( 2, st_done, next_state_rec, state_reg_rec );  
  fire event <array_index> fire[<integer>] create or select FIRE_EVENT    "fire event two" fe2  
  index <integer>
go to (<integer>|<state>)		 index <integer>
goto (<integer>|<state>)		 api call index
transition state when event is confirmed as received		   "goto state done" goto done  
  Register For Event Documentation     REGISTER_FOR_EVENT( 2, st_done, next_state_rec, state_reg_rec );  
  register for event <array_index> reg[<integer>] create or select REGISTER_FOR _EVENT    "register for event two" reg2  
  index <integer>
go to (<integer>|<state>)
trigger [time] <time>*		 index <integer>
goto (<integer>|<state>)
trigger <time>*		 api call index
transition state when event is received by any registration
optional simulation time to raise own event		   "goto state done" goto done  
  Transistion Documentation     TRANSITION( start, 20, ms(1), next_state_rec, state_reg_rec );  
  transition [<transition_integer>] tr[<integer>] create or select TRANSITION    "transition" tr  
  go to (<integer>|<state>)
(delay [count] | count) (<integer>|<time>)
divide [count] (<integer>|<time>)		 goto (<integer> | <state>)
(delay|count) (<integer>|<time>)
divide (<integer>|<time>)		 transition state when delay and divide counter values have been reached
delay counter terminal count (+1)
divide counter terminal count (+1)		   "goto state start"
"count twenty"
"divide one milli-second"		 goto start
count 20
divide 1ms		  
               
               
    STATEMACHINE CONSTRUCTION API          
  State Machine Construction Documentation     SM0: case (state_reg) is
          when 0 =>    --<----
           when 1 =>
          when 2 =>
          when others =>
end case;		  
  configure state machine [<resource_index>]
state (<integer>| <state_name>)
remove state machine [<resource_index>]		 sm[<integer>]
(state|st) (<integer>|<state_name>)
(remove|rm) sm[<integer>]		 create or select state machine
create or select state machine state
remove state machine instancecreate or select state machine
create or select state machine state
remove state machine instance		   "configure state machine" sm0  
  (add | insert) <integer> [states]
make <integer> [states]
next state
last state		 (add | insert) <integer>
make <integer>
(next | n)
(last | previous | l | n)		 integer number of states to add to state machine
makes the state machine contain specific number of states
select next state
select previous state		   "add two states"
"make five states"
"next state"
"previous"		 add2
make 5
next
last
  
  -- name = <string>[, <string>, <string>...] name or rename states with user defined list of names   -- name = init, start, process, wait, done  
               
               
    EDGE DETECTION API (2)          
  Monitor Falling Edges Documentation     MONITOR_RISING_EDGES( 0, control_input(0), st_reset, next_state_rec, state_reg_rec );  
  monitor falling [edges] <array_index> mf[e][<integer>] create or select MONITOR_FALLING_EDGES   "monitor rising edges zero" mre  
  index <integer>
go to (<integer>|<state>)
data <std_logic>		 index <integer>
goto (<integer> |<state>)
data <std_logic>		 api call index
transition state when falling edge is detected
input std_logic signal to monitior for falling edge		   "data control input zero"
"goto state reset"		 data control_input(0)
goto reset		  
  Monitor Risisng Edges Documentation     MONITOR_FALLING_EDGES( 0, control_input(0), st_reset, next_state_rec, state_reg_rec );  
  monitor rising [edges] <array_index> mr[e][<integer>] create or select MONITOR_RISING_EDGES    "monitor falling edges zero' mfe  
  index <integer>
go to (<integer>|<state>)
data <std_logic>		 index <integer>
goto (<integer> |<state>)
data <std_logic>		 api call index
transition state when rising edge is detected
input std_logic signal to monitior for rising edge		   "data control input zero"
"goto state reset"		 data control_input(0)
goto reset		  
               
               
    SHIFT REGISTER API (4)          
  Reset Left Shifter Documentation     RESET_LEFT_SHIFTER( next_state_rec(2), state_reg_rec(2) );  
  reset [left] shifter [<resource_index>] xl[<integer>] create or select RESET_LEFT_SHIFTER    "reset left shifter two" xl2  
               
  Reset Right Shifter Documentation     RESET_RIGHT_SHIFTER( next_state_rec, state_reg_rec );  
  reset right shifter [<resource_index>] xr[<integer>] create or select RESET_RIGHT_SHIFTER   "reset right shift register" xlr  
               
  Shift Data Left Documentation     SHIFT_DATA_LEFT(input_vector, 8, next_state_rec, state_reg_rec );  
  shift data left sdl create or select  SHIFT_DATA_LEFT   "shift data left" sdl  
  data <std_logic_vector>
shift <integer>
enable <std_logic>*
option (sign_extend|rotate|default)*		 data <std_logic_vector>
shift <integer>
enable <std_logic>*
[option] (sign_extend |rotate|default)*		 input data to be shifted to the left
number of bits to shift input data
enabl std_logic signal for shifter
optional enumeration to sign_extend or rotate		   "data input vector"
"shift eight"		 data input_vector
shift 8		  
  Shift Data Right Documentation     SHIFT_DATA_RIGHT( input_vectort, 8, next_state_rec, state_reg_rec );  
  shift data right sdr create or select  SHIFT_DATA_RIGHT   "shift data right" sdr  
  data <std_logic_vector>
shift <integer>
enable <std_logic>*
option (sign_extend|rotate|default)*		 data <std_logic_vector>
shift <integer>
enable <std_logic>*
[option] (sign_extend |rotate|default)*		 input data to be shifted to the right
number of bits to shift input data
enabl std_logic signal for shifter
optional enumeration to sign_extend or rotate		   "data input vector"
"shift eight"		 data input_vector
shift 8		  
               
               
    COMPONENT CONSTRUCTION API          
  Component Instantiation Documentation     input_converter: input_converter_0
  PORT (
    aclk : IN STD_LOGIC;
    aresetn : IN STD_LOGIC;
    s_axis_tvalid : IN STD_LOGIC;
    s_axis_tready : OUT STD_LOGIC;
    s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    m_axis_tvalid : OUT STD_LOGIC;
    m_axis_tready : IN STD_LOGIC;
    m_axis_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
  );
  
  add [component] <component_name>
remove [component]  <component_name> [<array_index>]		 add <component_name>
(remove|rm) <component_name>_<index>		 create new component instance
remove component instance		   "add input converter"
"remove input converter"		 add input_converter
remove input_converter
  
               
               
               
    HELPER API (2)          
  Disable File Documentation     DISABLE_FILE( next_state_rec, state_reg_rec );  
  disable file
disable (all|other) files		 disable file
disable (all|other)		 create DISABLE_FILE procedure call
disable all other files except current file		   "disable file"
"disable all files"		 df
disable all		  
               
  Resource Select Documentation     RESOURCE_SELECT( sys_clock, next_state_rec(1), state_reg_rec(1) );  
  resource select [<resource_index>] rs[<integer>] create or select RESOURCE_SELECT procedure call   "resource select one" rs1  
  clock (sys_clock |<clock_frequency>) clock (sys_clock |<clock_frequency>) clock domain clock frequency in Hz   "clock one hundred mega-hertz" clock 100E6  
               
  AXI Stream Interface Documentation          
    PRODUCTIVITY API          
  "loopback[(data|<module_name>)]"
axi <component_name>[<array_index>][<channel_name>]		 loopback[(data|<module_name>)]
axi <component_name>[<array_index>][<channel_name>]		 creates both READ_FIFO_DATA and WRITE_FIFO data calls
conntects framework fifo to axi stream port channels
   "loopback data"
"axi fft"		 loopback
axi fft